Patents Examined by Brett Feeney
  • Patent number: 10422642
    Abstract: A sensor comprises a substrate 16 and a sensor element 20 anchored to the substrate 16, the substrate 16 and sensor element 20 being of dissimilar materials and having different coefficients of thermal expansion, the sensor element 20 and substrate 16 each having a generally planar face arranged substantially parallel to one another, the sensor further comprising a spacer 26, the spacer 26 being located so as to space at least part of the sensor element 20 from at least part of the substrate 16, wherein the spacer 26 is of considerably smaller area than the area of the smaller of face of the substrate 16 and that of the sensor element 20.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: September 24, 2019
    Assignee: Atlantic Inertial Systems Limited
    Inventor: Christopher Paul Fell
  • Patent number: 10128346
    Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jun Kim, Sung-Dae Suk
  • Patent number: 10109792
    Abstract: A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 23, 2018
    Assignee: SK HYNIX INC.
    Inventor: Hyung Dong Lee
  • Patent number: 10109716
    Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vibhor Jain, Qizhi Liu, John J. Pekarik
  • Patent number: 9997533
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 9997737
    Abstract: A structure including a first resin layer and a second resin layer sandwiching a self-light emitting element layer, a first stopper layer, a first resin sacrificial layer and a first glass substrate which are stacked on the first resin layer on the opposite side of the self-light emitting element layer, and a second glass substrate stacked on the second resin layer is prepared. The first glass substrate is peeled off from the first resin sacrificial layer by irradiating the first glass substrate with a laser beam. The first resin sacrificial layer is decomposed by a chemical reaction using a gas. The first stopper layer has a resistance to the chemical reaction, and the first resin sacrificial layer is removed while leaving the first stopper layer in a step of decomposing the first resin sacrificial layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Japan Display Inc.
    Inventors: Kazufumi Watabe, Hiroshi Kawanago
  • Patent number: 9991360
    Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor layer over a substrate and forming an aluminum-silicon nitride layer upon the semiconductor layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 5, 2018
    Assignee: CORNELL UNIVERSITY
    Inventors: James R. Shealy, Richard Brown
  • Patent number: 9991202
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino
  • Patent number: 9981842
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 9969613
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 9938137
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 9932222
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Brigham, Christopher V. Jahnes, Cameron E. Luce, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, Eric J. White
  • Patent number: 9911654
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Plasma-Therm LLC
    Inventors: Linnell Martinez, David Pays-Volard, Chris Johnson, David Johnson, Russell Westerman, Gordon M. Grivna
  • Patent number: 9899387
    Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung
  • Patent number: 9852983
    Abstract: A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the first conductive plug; forming an amorphous silicon layer on the substrate, wherein a portion of the amorphous silicon layer overlapping the first conductive plug is defined as a first region, and a portion of the amorphous silicon layer overlapping the second conductive plug is defined as a second region; performing an implantation process to the first region and the second region, wherein the first region has a higher doping concentration than the second region; forming a titanium nitride layer on the amorphous silicon layer; and patterning the titanium nitride layer and the amorphous silicon layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Dai Yang Lee
  • Patent number: 9796045
    Abstract: Wafer alignment with restricted visual access has been disclosed. In an example, a method of processing a substrate for fabricating a solar cell involves supporting the substrate over a stage. The method involves forming a substantially opaque layer over the substrate. The substantially opaque layer at least partially covers edges of the substrate. The method involves performing fit-up of the substantially opaque layer to the substrate. The method involves illuminating the covered edges of the substrate with light transmitted through the stage, and capturing a first image of the covered edges of the substrate based on the light transmitted through the stage. The method further includes determining a first position of the substrate relative to the stage based on the first image of the covered edges. The substrate may be further processed based on the determined first position of the substrate under the substantially opaque layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 24, 2017
    Assignee: SunPower Corporation
    Inventor: Thomas Pass
  • Patent number: 9786597
    Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9786822
    Abstract: A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 10, 2017
    Inventor: Mordehai Margalit
  • Patent number: 9780190
    Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peide Ye, Zhiyuan Cheng, Yi Xuan, Yanqing Wu, Bunmi Adekore, James Fiorenza
  • Patent number: 9773707
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Guilei Wang, Jinbiao Liu, Jianfeng Gao, Junfeng Li, Chao Zhao