Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract: A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.

Abstract: A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile.

Abstract: A manufacturing method of an organic light emitting device may include the following. A panel displaying an image is formed. A buffering member including a dummy buffering member is adhered to the panel. A film is adhered to an upper surface of the buffering member. The film and the dummy buffering member are removed.

Abstract: A wiring substrate is provided with a first wiring layer including a first land, a first insulative layer formed on the first wiring layer, a second wiring layer formed on the first insulative layer, a second insulative layer formed on the second wiring layer, and a via formed extending through the first insulative layer and the second insulative layer in a thicknesswise direction. The via includes one end, which is electrically connected to the first land of the first wiring layer, and another end, which is located opposed to the one end and serves as a pad to which a mounted electronic component is electrically connected. The second wiring layer includes a coupling portion electrically connected to the via. The coupling portion of the second wiring has a width that is smaller than a diameter of the via.

Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

Abstract: The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.

Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

Abstract: A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract: The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers.

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Abstract: A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

Abstract: One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).

Abstract: An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.

Abstract: A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.

Abstract: An organic electroluminescent display device includes: a substrate; plural anodes that are formed in respective pixels; pixel separation films that cover at least an edge of the respective anodes between the respective pixels; an organic layer that covers a display area over the plurality of anodes, and the pixel separation films, and includes at least a light emitting layer; a cathode that is formed on the organic layer; and a counter substrate that is arranged on the cathode so as to face the substrate, in which the anodes each include: a contact area that comes in contact with the organic layer, and faces a corresponding pixel of the counter substrate, and a peripheral area that is formed around the contact area, and faces pixels around the corresponding pixels of the counter substrate. The organic electroluminescent display device can realize higher definition, higher luminance, and prevention of color mixture.