Abstract: A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns.

Abstract: A metal structure, such as an apparatus used in plasma processing of substrates, is rendered resistant to corrosion by coating components exposed to the plasma with a coating of rhodium. The rhodium coating can be made by electroplating, and preferably has a thickness of at least about 10 microinches, and preferably from about 10 to about 100 microinches. A coating of nickel can be applied between the rhodium coating and the metal component.

Abstract: A metal oxide semiconductor field effect transistor with a lightly doped silicon substrate includes an oppositely doped well and oppositely doped source region and oppositely doped drain region with respect to the lightly doped substrate, the improvement comprising at least one counter doped region formed along the surface of the oppositely doped well between the source and drain regions. The substrate comprises a P-substrate, the well comprises an N- well and the counter doped region is doped P; the counterdoped region comprises an island among a plurality of islands between the source region and the drain region. The counterdoped region comprises an island among a plurality of islands between the source region and the drain region.

Abstract: There are provided a treatment chamber for removing natural oxide films formed on the surface and the underside of an object to be treated, e.g., a semiconductor wafer, in treating gas ambient atmosphere, holding member for holding the object to be treated in the treatment chamber, and a mounting member with, e.g., pins erected thereon, and a disk body disposed inside the mounting member. The mounting member and the disk body are rotated relatively to each other. The relative rotation of the mounting member and the disk body generates flows of the treating gas, so that the natural oxide films are homogeneously removed from the entire surface and underside of the object to be treated.

Abstract: A method and apparatus for reducing particulates in a plasma tool using steady state flows includes a device, operatively coupled to a housing in which an object to be processed is positioned, for generating a plasma flow adjacent the object toward a pumping aperture. A pumping mechanism pumps a medium adjacent the object. The medium supports the plasma and entrains particulates in the plasma away from the object and out the pumping aperture. Magnetic fields, produced by multipole magnets forming a ring cusp, are preferably used to produce the plasma flow which is directed radially away from the object to be processed. In a second embodiment, an array of magnets which form a line cusp is provided to produce an opening through which plasma will flow.

Abstract: A method for manufacturing electrostatic discharge (ESD) devices on a silicon substrate. The method is consistent with fabricating an integrated circuit having a buried contact structure. By modifying photolithographic masks, the ESD device and the buried contact are formed on the silicon substrate at the same time. Without any extra processing steps, the manufacturing of the ESD device is simplified thus reducing the manufacturing cost.

Abstract: A semiconductor device which has a resistor, a capacitor, a Schottky diode, and an ESD protection device all formed on a single semiconductor substrate. The resistor and the capacitor are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor and capacitor.

Abstract: A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Abstract: A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed through a polysilicon gate structure, into the underlying channel region. The ability to reproducibly place the desired dopant at the desired channel location, is dependent on the implant conditions as well as the reproducibility of the thicknesses of the layers the implant has to penetrate. This process has been designed to remove some of the variables and thus result in optimized device characteristics.

Abstract: A method of fabricating a MESFET is comprised of providing a semiconductor material having a channel region formed therein, forming a gate on the semiconductor material over the channel region, forming a spacer adjacent a first portion of the gate disposed on the semiconductor material, and forming a hard mask disposed on a second portion of the gate and on a portion of the semiconductor material.

Abstract: A self-aligned gate sidewall spacer and method of forming the sidewall spacer in a corrugated FET structure, comprising the steps of depositing a first oxide layer on a substrate; forming a substrate trench, having a substrate trench bottom and substrate trench sidewalls in the substrate; forming a gate electrode trench intersecting the substrate trench and filling the gate electrode trench with gate polysilicon for forming a gate electrode, the gate electrode having first and second gate sidewalls; depositing a second oxide layer over the gate electrode trench and substrate trench; and etching the second oxide layer for forming a sidewall spacer on each of the first and second gate sidewalls.

Abstract: In a CVD processing system for depositing a blanket tungsten film, a distinct shadow is formed without causing any micro-peeling when the substrate fixture is separated from the substrate so as to prevent any blanket tungsten from being deposited on SiO.sub.2, thus reducing the occurrence of fine dust particles.

Abstract: A method for fabricating gate oxide layers of different thicknesses on a silicon substrate. A field oxide layer is formed on a predetermined portion of the silicon substrate to define first active regions and second active regions. A first gate oxide layer is formed over the first and second active regions. A barrier layer is formed to cover a portion of the first gate oxide layer within the first active regions. The portion of the first gate oxide layer within the second active regions is then removed utilizing the barrier layer as masking. A second gate oxide layer is then formed over the second active regions.

Abstract: A novel semiconductor fabrication chamber includes a quartz vessel and a metal vessel with a resilient sealing member disposed between the quartz and metal vessels to define a vacuum chamber, along with a cooling assembly mounted on a quartz flange extending around the perimeter of the quartz vessel. A liquid or gaseous cooling medium is passed through the cooling assembly to reduce the operating temperature of a portion of the resilient sealing member in contact with the quartz flange during semiconductor fabrication processing so as to extend the useful life of the sealing member. The cooling assembly is secured to the quartz flange using a plurality of clamping fixtures for easy installation and retrofitting.

Abstract: An apparatus for producing a compound semiconductor layer includes a first flow rate controller for adjusting flow rates of respective material source gases, a gas mixing pipe for mixing the respective material source gases, gas distributing pipes for distributing gases and connected to the gas mixing pipe, a second flow rate controller for adjusting flow rates of the material source gases flowing through the gas distributing pipes and for supplying the material source gases to a reaction tube, a pressure detector for detecting pressure in the gas mixing pipe, and a third controller responsive to the pressure detector for controlling the second flow rate controller to maintain a constant pressure in the gas mixing pipe. Retardation of the gases between the first and second flow rate controllers is avoided, improving thickness uniformity in grown layers.

Abstract: The described embodiments of the present invention provide a method for fabricating elevated source/drain junction metal oxide semiconductor field-effect transistors. The process does not require the use of selective or epitaxial silicon growth processes. In one embodiment, first a three layer gate stack is formed having a gate dielectric layer (20) beneath a polycrystalline silicon gate layer (22) and a disposable spacer layer (24), such as silicon nitride formed on top of the polycrystalline silicon gate. A conformal dielectric layer is formed overall and anisotropically etched to form sidewall spacers layers (26) on the sides of the gate, and spacer layer stack. The spacer layer (24) is then selectively removed and a layer of amorphous or polycrystalline silicon (30) is deposited overall. A layer of silicon nitride is then deposited on the surface of the polycrystalline silicon layer using chemical-vapor deposition techniques.

Abstract: End members are located at the top and the bottom of a vertical heat treatment device. A plurality of support members are vertically mounted on the end members. A plurality of wafer hold members are fixed on the support members in a parallel manner, each of which is formed in an approximately circular arc shape. The wafer hold member is made of SiC by a CVD method or Si3N4 by a CVD method. The wafer hold member has a plate portion on which a wafer is to be placed and a reinforce portion connected to the plate portion. The plate portion is 100-1000 microns in thickness.

Abstract: In a CVD processing system for depositing a blanket tungsten film, a distinct shadow is formed without causing any micro-peeling when the substrate fixture is separated from the substrate so as to prevent any blanket tungsten from being deposited on SiO.sub.2, thus reducing the occurrence of fine dust particles.

Abstract: A process of fabricating a bi-CMOS integrated circuit device has a step of selectively growing doped polysilicon over a source/drain region and a part of base region exposed to contact holes formed in a silicon oxide layer without residue of the doped polysilicon on the silicon oxide layer, thereby preventing the bi-CMOS integrated circuit device from undesirable short circuit.

Abstract: The invention provides a method for fabricating a solid imaging device in which an insulation film including at least a silicon oxide film deposited by a chemical vapor deposition method is formed on a surface of the device. An exposed part of the insulation film may be etched prior to forming a shield film, thereby preventing an incident light to enter into all surface of the device except for a photoelectric conversion region.