Abstract: A silicon quantum wire transistor. A silicon substrate is sub-etched leaving a thin ridge (.ltoreq.500 .ANG. tall by .ltoreq.500 .ANG. wide) of silicon a quantum wire, on the substrate surface. An FET may be formed from the quantum wire by depositing or growing gate oxide and depositing gate poly. After defining a gate, the source and drain are defined. Alternatively, an optically activated transistor is formed by defining an emitter and collector and providing a path for illumination to the wire.

Abstract: An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Abstract: An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.

Abstract: A Field Effect Transistor having a recessed gate comprises a substrate, a source electrode and a drain electrode, a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate electrode inclined toward the source electrode and formed over the recessed channel portion.

Abstract: An apparatus to retain integrated circuit modules during the preparation for a cycling of temperature, during the cycling of temperature, and during the post-handling after the cycling of temperature, is described. The apparatus has a specimen basket to contain the integrated circuit modules, a plurality of specimen retaining rods coupled to the specimen basket to prevent the integrated circuit modules from movement within the basket, a plurality of integrated circuit module retaining means coupled to the specimen retaining rods to secure each of the integrated circuit modules within in the specimen basket, and a specimen securing rod retaining means to fasten each of the specimen retaining rods to the specimen basket.

Abstract: Charge couples devices and methods for the fabrication of the same are disclosed.The charge coupled device is structured to comprise: a first electrode consisting of a first region and second region having lower resistance than the first region; and a second electrode consisting a first region and a second region having lower resistance than this first region, the first region of the first electrode being adjacent to said first region of the second region at an interval of an insulating film.Capable of utilizing the force of electrical field, the charge coupled device is superior in charge transfer efficiency as well as charge transfer velocity.In addition, it has capability to improve the performances of high picture quality solid state image sensing device as well as time delay device, which both necessitate a charge coupled device and operates at high frequencies.

Abstract: Plasma reactors are used extensively in the manufacture of integrated circuits for the deposition and etching of thin films at low temperatures. Their range of operating temperatures and gas pressures make them highly susceptible to build-up of deposits on the inner surfaces of the reaction chamber which subsequently become dislodged by vibrations, stresses, and other aggravations and are dispersed within the system as particulates. The monitoring of particulate accumulation on wafers is conventionally done by subjecting a test wafer to a simulated operation within the tool under gas flow alone. Some types of plasma reactors incorporate oscillating gas dispersion housings in order to improve homogeneity of the gas mixture. The motion of these housings can induce significant particle displacement within the chamber. The correct monitoring procedure for these tools must therefore include the motion of the distribution housing in addition to the conventional procedures.

Abstract: An element separating oxide film is formed on a P-type semiconductor substrate by means of a selective oxidation method, and then a gate oxide film is formed on the element separating oxide film by a thermal oxidation method. A gate electrode film made of an N-type polysilicon material is formed so as to extend along a step portion of the element separating oxide film on the semiconductor substrate. The upper surface of the gate electrode film is flattened by means of a surface polishing method. Then, isotropic etching is performed by using a resist pattern as a mask, thereby forming a gate electrode. Since in the method the upper surface of the gate electrode film in the flattened, the semiconductor substrate is prevented from being subject to over-etching when a gage electrode is formed, so that the changes of characteristics of MOS transistors are prevented whose gate insulative films have been becoming thinner as their elements have been finer.

Abstract: An N-type source (or drain) region is formed in the surface area of a P-type silicon substrate. A first insulation film is formed on the silicon substrate and a gate electrode is formed on the first insulation film. A second insulation film is formed on the first insulation film and gate electrode. A through hole is formed in those portions of the second insulation film, gate electrode and first insulation film which lie on the source region. A gate oxide film is formed on the side wall of the through hole. A P-type silicon layer serving as a channel region is formed on that portion of the source region which lies inside the through hole by the selective epitaxial growth. An N-type drain (or source) region is formed in the upper portion of the silicon layer. A third insulation film is formed on the resultant structure.

Abstract: A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e.

Abstract: A high speed MOSFET device includes a punchthrough stopper region in the channel of the device formed by high energy ion implantation through the gate electrode and self-aligned therewith. The device has reduced capacitance. A self-aligned recessed channel MOSFET structure includes the punchthrough stopper region to further improve short channel device behavior.

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with limited susceptibility to Hot Carrier Effects (HCEs), and a method by which that MOSFET is formed. There is first provided a semiconductor substrate which has a first portion, a second portion adjoining a side of the first portion and a third portion adjoining an opposite side of the first portion. Formed upon the first portion of the semiconductor substrate is a gate oxide layer which has a gate electrode formed and aligned thereupon. The gate electrode has a first sidewall adjoining the second portion of the semiconductor substrate and a second sidewall adjoining the third portion of the semiconductor substrate. Formed upon the first sidewall of the gate electrode and upon the surface of the second portion of the semiconductor substrate adjoining the first sidewall is a conformal oxide layer. The conformal oxide layer has a dose of fluorine atoms incorporated therein.

Abstract: An ESD protection device and a method for forming the ESD protection device in an active region (13) which is devoid of a field oxide (14). A P type dopant region (22) and an N type dopant region (27) are formed in a semiconductor substrate (11) using photolithographic techniques, wherein they are spaced apart from each other by a spacer region (29). An anode electrode (33) contacts the P type dopant region (22) and a cathode electrode (34) contacts the N type dopant region (27). A parasitic diode resistance of the ESD protection device is governed by the width of the spacer region (29) which, in turn, is governed by the resolution of the photolithographic techniques. Thus, the present invention provides a method for lowering both the parasitic diode resistance and clamp voltage of the ESD protection device which serves to protect integrated circuits from large voltage transients.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: Transistor devices comprise a gate electrode, a channel region formed beneath the gate electrode, a source region in contact with one side of the channel region, a first conductive region formed in a semiconductor layer at the outer side of the source region and made of a metal or metal compound, a drain region formed in contact with the other side of the channel region, and a second conductive region formed in the semiconductor layer at the outer side of the drain region and consisting of a metal or a metal compound. The transistor has an SOI structure which has an improved breakdown voltage between the source region and the drain region with low sheet resistances of the source and drain regions. Methods for making the transistor devices are also described.

Abstract: A field effect transistor has (a) a channel layer formed by a non-doped first semiconductor material (b) an electron supply layer formed by a doped second semiconductor material having an electron affinity which is lower than the affinity of the first semiconductor material, and (c) a contact layer formed by a doped third semiconductor material having an electron affinity which is higher than the affinity of the second semiconductor material. These layers are successively formed on a substrate of semi-insulating semiconductor material. Ions are implanted and a surface side portion of the contact layer is removed in a region other than at active portions in order to retain at least a part at a substrate side of the contact layer. By this arrangement, an excellent isolation can be achieved without producing large steps due to the mesa shape. Leakage current is not produced. There is no deterioration of the pinch off characteristic and withstand voltage.

Abstract: One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

Abstract: There is described a process for making a P channel MOS gated device in which N.sup.- bases are first formed through a patterned polysilicon gate structure. A central N.sup.+ contact is then formed in the center of the surface of each N.sup.- base in a second non-critical mask step. A thermal oxide is then grown atop the N.sup.- and N.sup.+ surfaces of each base with differential thickness, the N.sup.+ surface region growing a thicker oxide. A P.sup.+ source implant is then carried out, penetrating only the thinner oxide over the N.sup.- surfaces. Contact openings are then formed in a third mask process and contact metal is deposited in contact with the P.sup.+ and N.sup.+ regions. A ring-shaped termination is simultaneously formed, using the same process steps.

Abstract: There are provided a solid state imaging device having high sensitivity and exhibiting high degree of light utilization and a method of manufacturing the same. An insulating film 42, a transfer electrode 43, a light shielding film 44, a protective film 45, and a flat layer 51 are formed above a layer having a photoelectric conversion portion, and a concave lens layer 52 is formed on the flat layer 51 to a lattice pattern. The concave lens layer 52 of the lattice pattern is hot melted for conversion into a concave type micro-lens 52. A resin layer 53 having a refractive index smaller than that of the concave lens 52, a buffer layer 54, and a convex type micro-lens 57 are sequentially formed above the concave type micro-lens 52. The concave type micro-lens 52 functions to bring light rays focused by the convex type micro-lens 57 to a position close to light incident vertically upon the photoelectric conversion portion 41.

Abstract: The method is characterized by the steps consisting in: a) producing a semi-insulating or n-type substrate; b) forming a separating layer of a p.sup.+ -type doped material on the surface of said substrate; c) forming an active layer on said separating layer, the active layer including at least a bottom layer with n-type doping; d) making a set of semiconductor components by etching and metalizing said active layer; g) fixing a common support plate on the assembly made in this way, thereby holding the components together mechanically; and h) dissolving the material of the separating layer anodically and without illumination while leaving the other materials intact, thereby separating the substrate from said components without dissolving the substrate.