Abstract: A method of making a signal charge transfer device, including the steps of: forming first conductivity-type channel regions (30) in each of second conductivity-type wells (20) formed in a first conductivity-type semiconductor substrate (10); forming a plurality of first electrodes (50a) uniformly spaced from one another, and then forming an insulation film (40) for insulating the first electrodes from one another; forming a primary potential barrier (70) in each of the channel regions by subjecting the channel regions to a primary-ion implantation process using the plurality of first electrodes as a mask; forming a secondary potential barrier (70a) in each of the channel regions at lower corners of each of the first electrodes by subjecting the channel regions to a sloped secondary-ion implantation process using the plurality of first electrodes as a mask; and forming second electrodes (80a), each being disposed between the adjacent ones of the first electrodes, and then forming an insulation film (60) to ins

Abstract: A high performance lateral Silicon-On-Insulator (SOI) power device having a high breakdown voltage (.ltoreq.100 v). The SOI power device includes a silicon layer formed on an oxide layer over a silicon substrate. A mask having a single opening on the anode (drain) side of the silicon layer is formed thereon such that an impurity may be introduced into the silicon layer. The resultant dopant is implanted in the anode side and laterally diffused by high temperature annealing. The resultant device sustains breakdown voltages of up to 100 volts and enables an extremely low on-state resistance of 1.2 milliohm-cm.sup.2.

Abstract: The present invention comprises a metal semiconductor field effect transistor (MESFET) 100. The MESFET 100 comprises a semiconductor substrate 110 composed of gallium arsenide (GaAs) which has a top surface. This MESFET transistor 100 further comprises a contiguous first conductivity type source area 165, gate area 164, and drain area 170 disposed near the top surface on the semiconductor substrate 110, wherein the source and drain areas 165 and 170 respectively are of an equal relatively large depth from the top surface with high doping concentration. The gate area 164 is of a relatively small depth from the top surface. The gate area 164 is further disposed between and extending thereunto the source area 165 and the drain area 170. The gate area 164 further includes a current enhancement region 155 being doped with ions of the first conductivity with relatively lower concentration and extending between the gate area 164 and the source area 165.

Abstract: A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

Abstract: A semi conductor wafer processing apparatus has a wafer supporting susceptor having a sealing surface, a susceptor drive shaft for connection to the susceptor also having a sealing surface, a seal disposed between the susceptor and drive shaft sealing surfaces having a rigid metallic core and a ductile metallic coating on the core, and fasteners connecting the susceptor to the drive shaft and compressing the seal between the susceptor and drive shaft sealing surfaces. The seal retains sealing capability upon being subjected to changes in temperature.

Abstract: A process for fabricating a MOS device having a recessed gate on a silicon substrate. Source/drain regions are formed by implanting impurities of a first conductivity type into a silicon substrate. A trench is formed in the silicon substrate, the trench being separated from the source/drain regions by side wall spacers on side walls of the trench. The source/drain regions extend to areas underlying the sidewall spacers. An anti-punchthrough region is formed by implanting impurities of a second conductivity type into a portion of the silicon substrate underlying the trench. A gate layer is formed within the trench, the gate layer being separated from the anti-punchthrough region by a gate oxide layer.

Abstract: A process for fabricating a MOSFET device, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The process features creating a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET, via ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.

Abstract: A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated ions. This is followed by forming openings in the shielding arrangement by microlithographic processes and anisotropic etching, and then implanting ions via the openings to form one of a base area and a base-connection area of the first conductivity type. Edges of the openings are displaced by isotropic etching of the lower part of the shielding arrangement.

Abstract: A vertically structured transistor and method for manufacturing the same achieves a highly integrated semiconductor device. A pillar is vertically formed on a semiconductor substrate and forms a channel region of the transistor. A gate electrode is formed in a self-alignment fashion so as to surround the sides of the pillar with a gate insulating film imposed therebetween. A source region and a drain region are formed in a lower portion and an upper portion of the pillar, respectively. The area occupied by a transistor according to the present invention is remarkably reduced.

Abstract: A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters.

Abstract: An improved structure and process of fabricating a metal oxide field effect (MOSFET) which has a high resistance to electro-static discharge. The device has pre-gate heavily doped source and drain regions which overlap the gate electrode and the source and drain regions. This improved MOSFET device with overlapping pre-gate source and drain regions is incorporated into an electro-static discharge (ESD) circuit to form a memory device which has a high resistance to electro-static discharge (ESD).The MOSFET device with pre-gate heavily doped source and drain regions can be formed as follows. Spaced pre-gate source and drain regions of a second conductivity type are formed in the substrate with a background doping of a first conductivity type. A gate oxide and a gate is formed in the regions between the pre-gate source and drain regions. The gate at least partially overhangs the pre-gate source and drain regions. Subsequently, spacers are formed on the vertical sidewalls of the gate.

Abstract: An output circuit device for detecting and converting signal charge transferred thereto from a charge transfer section of a CCD into a signal voltage and a method of forming same. A first diffusion region is formed by diffusing into the semiconductor body a low concentration of an impurity having a conduction type opposite to that of said semiconductor body and having a high diffusion coefficient. A second diffusion region is formed by diffusing into an upper surface portion of the first diffusion region, and in self-alignment therewith, a high concentration of an impurity having a low diffusion coefficient. A third diffusion region is formed by diffusing into the first and second diffusion regions, and in self-alignment therewith, a high concentration of an impurity having a high diffusion coefficient, such that the third diffusion region extends from a surface of said semiconductor body through said first and second diffusion regions to beneath the first diffusion region.

Abstract: A solid state image sensor device includes: a photoelectric conversion section having a first conductivity type semiconductor thin region and a second conductivity type semiconductor region in a surface area of a first conductivity type semiconductor layer; a signal electron transfer section formed within the surface area of the first conductivity type semiconductor layer, for transferring a signal electron generated at the photoelectric conversion section; and a signal electron read-out section formed over the surface area of the first conductivity type semiconductor layer, for reading-out the signal electron from the photoelectric conversion section to the signal electron transfer section. The first conductivity type semiconductor thin region is self-aligned with respect to the second conductivity type semiconductor region and this is achieved by using the same mask and controlling the angles of incidence in the ion implantation.

Abstract: A recording head for discharging ink by using thermal energy comprises a plurality of outlets for discharging ink and a substrate including a common substrate plate of P type, a plurality of electrothermal converting elements and a plurality of functional elements connected to the respective electrothermal converting elements and formed on the common substrate plate as well as the electrothermal converting elements. Each of the functional elements has a first semiconductor region of N type, a second semiconductor region of P type provided within the first semiconductor region and a third semiconductor region of N type provided within the second semiconductor region, so as to form a rectifying junction. The first, second and third semiconductor regions are formed by diffusion of impurity atoms in the common semiconductor substrate plate.

Abstract: A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.

Abstract: A process for forming retrograde and oscillatory profiles in crystalline and polycrystalline silicon. The process consisting of introducing an n- or p-type dopant into the silicon, or using prior doped silicon, then exposing the silicon to multiple pulses of a high-intensity laser or other appropriate energy source that melts the silicon for short time duration. Depending on the number of laser pulses directed at the silicon, retrograde profiles with peak/surface dopant concentrations which vary from 1-1e4 are produced. The laser treatment can be performed in air or in vacuum, with the silicon at room temperature or heated to a selected temperature.

Abstract: In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region and a drain region may also be arranged on the same plane and the latter MOS device Is arranged to the gate electrode. This the of device may be constructed as a CMOS type device.In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.

Abstract: A method for fabricating a solid-state image sensing device wherein a plurality of sensor regions are arranged in two-dimensions. A plurality of vertical transfer lines are associated with respective vertical rows of the plurality of sensor regions to transfer signal charges read from the sensor regions. A gate electrode is formed on an insulating layer over a signal charge transfer layer formed at the surface of the substrate. A buffer layer is formed containing hydrogen on an interlayer insulating layer over the gate electrode and the sensor regions. The light shielding layer is formed only over the buffer layer.

Abstract: The present invention provides a novel method for fabricating an isolation region involved in a semiconductor device. An active region of a first conductivity type is selectively formed in a predetermined area in a semiconductor layer of a second conductivity type. A metal film over said active region is selectively formed without use of any heat treatment to prevent said active region from suffering any damage due to heat treatment. A selective ion-implantation of an impurity of the second conductivity type is carried out by use of said metal film as a mask to form an isolation region of a higher impurity concentration than an impurity concentration of said second conductivity type semiconductor layer.

Abstract: The present invention provides the method of manufacturing a dual-gate CMOS device which has high transconductance and improved breakdown voltage, in which depletion in the interface between a gate oxide and a gate electrode is prevented without the increase of the steps of process.A gate oxide film (5) formed on a semiconductor substrate (1) is washed with an aqueous solution, or exposed to a gas atomosphere containing hydrogen, and an amorphous silicon film (3) is formed on the whole surface of the gate oxide film (5). The amorphous silicon film (3) is then crystallized. Alternatively, after a silicon oxide film (53) or a silicon nitrided film is formed on the amorphous silicon film (3), the amorhpous silicon film (3) is crystallized.