Abstract: One embodiment is a method that segments a bus topology to increase addressable devices that can attach to a bus. Switching occurs between different segments on the bus having multiple bus segments linked together.

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device has an output. Furthermore, a housing with a plurality of assignable external pins and a protected pin ownership logic for each assignable external pin is provided and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: Various exemplary embodiments relate to a function selector device in a system using a DisplayPort protocol over a universal serial bus (USB) mechanical interface, including: a first port configured to transmit/receive a USB SSTX signal; a second port configured to transmit/receive a USB SSRX signal; a third port configured to transmit/receive a DisplayPort lane signal; a fourth port configured to transmit/receive a DisplayPort AUX signal; a fifth port configured to transmit/receive a DisplayPort HPD signal; a sixth port configured to connect to SSTX pins of a USB 3.0 receptacle; and a seventh port configured to connect to SSRX pins of a USB 3.0 receptacle.

Abstract: A military standard-1760 (MIL-STD-1760) interface bridge can include a housing, a translator device, and an energy storage device. The housing can include a MIL-STD-1760 connector on a first end and a weapon side connector on a second end. The translator device can translate a MIL-STD-1553B remote terminal (RT) protocol to a weapon side signaling protocol and translate the weapon side signaling protocol to the MIL-STD-1553B RT protocol. The energy storage device can be coupled to the operating power of the MIL-STD-1760 connector and can be configured to provide power to the translator device for a duration after the power from the MIL-STD-1760 connector is disconnected.

Abstract: A universal serial bus stack may use an emulation layer to grant a non-universal serial bus device access to universal serial bus drivers and applications. The universal serial bus stack may exchange a device communication at an emulation layer. The universal serial bus stack may translate between a universal serial bus communication and the device communication at the emulation layer, and then may exchange the universal serial bus communication at a universal serial bus client interface.

Abstract: Certain aspects of the disclosure relates to a method for operating an electronic device. A control device detects a Universal Serial Bus (USB) interface being connected to the electronic device, where the USB interface has a plurality of virtual ports. Then the control device receives one or more descriptors through the USB interface, each descriptor corresponding to a function of the electronic device. Then the control device matches each descriptor corresponding to each function with one driver file corresponding to each function, and after the matching is successful, determines a virtual function device corresponding to execution of each function. In response to receiving an operating command for executing one function, the control device sends the operating command to the corresponding virtual function device to the function to be executed through a corresponding driver interface, such that the corresponding virtual function device is operated on the electronic device.

Abstract: A system for bidirectional signal transmission may comprise a forward data transmission circuit to unidirectionally transmit a first input signal and a backward data transmission circuit to unidirectionally transmit a second input signal. The backward data transmission circuit may comprises a logic circuit to detect a voltage difference over a resistance element in the forward data transmission circuit. When the voltage difference is lower than a threshold value, the logic circuit outputs a first voltage level. When the voltage difference is greater than or equal to a threshold value, the logic circuit outputs a second voltage level different from the first voltage level.

Abstract: A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor.

Abstract: A mated pair of Universal Serial Bus (USB) wireless dongles are disclosed. The dongles comprise a first USB dongle that comprises a first processor, a first read only memory (ROM) storing an address of a second USB dongle, a first radio transceiver, a first USB connector, and a first application. When executed by the first processor, the first application receives a USB formatted message from the first USB connector; transcodes the USB formatted message for wireless transmission; transmits the transcoded message to the address of the second dongle. The dongles further comprise the second dongle, which comprises a second processor, a second ROM storing an address of the first dongle, a second radio transceiver, a second USB connector, a second application that, when executed by the second processor, receives the message from the first dongle; confirms that the first USB is its mate; and communicates with the first dongle.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

Abstract: An electronic device includes a battery, a detecting unit, a comparing unit, a control unit and a charging circuit. The detecting unit is electronically connected to a universal serial bus (USB) interface to detect and determine whether or not the connecting device is a power adapter. The comparing unit outputs a level signal depending upon the comparing unit comparing a input signal received by the USB interface with a voltage threshold. The control unit controls the battery either to be charged by the connecting device through the charging circuit or the battery to supply power to the connecting device through the USB interface according to the level signal.

Abstract: A power control method of an electronic device is provided. The method includes receiving a power-on event in a power-off state of the electronic device and determining whether the received power-on event is a real time clock (RTC) interrupt. The method further includes determining, if the power-on event is the RTC interrupt, whether the power-off state is caused by an abnormal power-off, and performing, if the power-off state is caused by the abnormal power-off, a booting procedure.

Abstract: Embodiments of the present invention disclose a method and apparatus for processing a cluster in a cluster system, and a cluster system, relate to the field of communications technologies, and are invented for effectively simplifying a cluster system. The method includes: sending, by switched fabric board of a member device, a request answer signal for requesting a main control board that receives the request answer signal to answer the request answer signal; and if the switched fabric board do not receive an answer signal of the request answer signal, sending, by the switched fabric board, an address of a main monitoring module to a main control board of a main device. The present invention may be applied to a clustering technology.

Abstract: Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface configured to communicatively connect to a computing device. The system may also include a multi-channel interface configured to communicatively connect to multiple subrate channels. Further, the system may include a controller configured to communicatively connect the subrate channels with the computing device via the USB interface. The controller may also be configured to communicate, to the computing device, connection specifications for the subrate channels.

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Abstract: An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

Abstract: A mechanism is provided for switching a locking mode of an object in a multi-thread program. The mechanism acquires, during execution of the program, access information related to accesses to the object by a plurality of threads. The object supports a single-level locking mode and a multi-level locking mode. The single-level locking mode is a mode capable of locking the object. The multi-level locking mode is a mode capable of locking the object and fields in the object respectively. The mechanism switches the locking mode of the object between the single-level locking mode and the multi-level locking mode based on the access information.