Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract: A mechanism is provided for switching a locking mode of an object in a multi-thread program. The mechanism acquires, during execution of the program, access information related to accesses to the object by a plurality of threads. The object supports a single-level locking mode and a multi-level locking mode. The single-level locking mode is a mode capable of locking the object. The multi-level locking mode is a mode capable of locking the object and fields in the object respectively. The mechanism switches the locking mode of the object between the single-level locking mode and the multi-level locking mode based on the access information.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

Abstract: A computing machine to power a memory to retain a process state of the computing machine if the computing machine is in a sleep state and transfer the process state from the memory to a non-volatile storage device, where the computing machine remains in the sleep state as the process state is transferred from the memory to the non-volatile storage device.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

Abstract: A method of matching signal transmission between two electronic devices connected to one another with a physical interface and each have a transmitter and a receiver, wherein signals are transmitted from the transmitter of one device along a transmission link to the receiver of the other device and wherein the transmission link has at least two signal lines (+, ?) for differential transmission of the signals including A) detecting signal values on the receiver of the first device separately for each of the two signal lines (+, ?), B) evaluating a mismatch between the signals from the two signal lines (+, ?) on the receiver of the first device on the basis of the detected signal values, and C) changing one or more parameters of the transmitter in the second device for at least one of the two signal lines (+, ?), wherein at least A) and C) are performed iteratively until a predetermined termination criterion is satisfied.

Abstract: Structure is disclosed for a non-blocking SAS architecture utilizing virtual connections between SAS devices. One embodiment comprises a SAS expander. The SAS expander comprises a plurality of physical links (PHYs) and a Virtual Connection Manager (VCM) coupled with the plurality of PHYs. The VCM exchanges information over a plurality of concurrently established virtual pathways between a first PHY of the plurality of PHYs and a second PHY of the plurality of PHYs.

Abstract: The present disclosure includes a medical monitoring hub as the center of monitoring for a monitored patient. The hub includes configurable medical ports and serial ports for communicating with other medical devices in the patient's proximity. Moreover, the hub communicates with a portable patient monitor. The monitor, when docked with the hub provides display graphics different from when undocked, the display graphics including anatomical information. The hub assembles the often vast amount of electronic medical data, associates it with the monitored patient, and in some embodiments, communicates the data to the patient's medical records.

Abstract: Method of communication between a host device, a first client device, a second client device and one or more peripheral devices and host device for use in such method, the host device comprising communication means for communicating with the client device and the one or more peripheral devices; a processor/controller connected to a memory suitable for storing configuration information and for controlling the communication means, the host device adapted to providing information in a wireless network with respect to availability of one or more sets of the peripheral devices to be connected with the client device; receiving via the wireless network a request from a first client device to connect to a first set of peripheral devices; determining that the first client device is docked to the first set; determining a second set of peripheral device that are free/available for connection to a second client device while the first client device is docked; providing information in the wireless network with respect to t

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing units comprising a processor, a memory coupled to the processor, and a communication port configured to coupled to a backbone communication network of a control system. The memory stores a program that causes the processor to selectively participate (over the communication port) as a processing unit of a control system of a first manufacturer (the control system implements a first proprietary communication protocol between processing units), and to participate (over the communication port) as a processing unit of a control system of a second manufacturer different than the first manufacturer (the control system of the second manufacturer implements a second proprietary communication protocol between the processing units).

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: A system-on-chip including an ingress arbiter module to receive a plurality of service requests from a plurality of devices located upstream to access a resource located downstream. Each of the service requests includes a quality of service value and a first timing budget value specified by the respective device to indicate an amount of time in which the respective service request is to be serviced by the resource. The ingress arbiter module selects a first service request based on the quality of service values, the first timing budget values, and a time delay associated with arbitrating the plurality of service requests and outputting the first service request downstream. A timing budget generator module generates a second timing budget value for the first service request based on the first timing budget value associated with the first service request, and the time delay.

Abstract: A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB host is configured to wirelessly transmit a beacon over a wireless USB network based on a wireless USB protocol. The first and second wireless USB devices are configured to exchange wireless packets with the wireless USB host. The beacon designates the wireless USB network address access times for the first and second wireless USB devices.

Abstract: In a communication system, a master device gives a data control to one of a plurality of slave devices, and stops controlling data transmission and reception in the master device. A dual-role device executes the data transmission and reception with the other slave devices according to the data control given by the master device. The master device transmits an abort signal to the dual-role device while data is being transmitted and received by the dual-role device according to the data control. The dual-role device receives the abort signal from the master device, and transmits an interrupt signal to the master device when no data is being transmitted or received. The master device enables data transmission and reception according to the data control after receiving the interrupt signal from the dual-role device. The dual-role device stops data transmission and reception according to the data control after receiving the interrupt signal.

Abstract: A method and system for configuring at least one communication interface module in a control or automation system includes a communication interface module for coupling at least two field bus systems. At least one first functional unit integrated in the communication interface module implements a connection to a configured superordinate controller via a first communication link on the basis of a first field bus protocol. At least one second functional unit integrated in the communication interface module implements a connection for field devices via a second communication link on the basis of a second field bus protocol. At least one further, third functional unit integrated in the communication interface module is configured to connect further field devices via input and/or output functionalities integrated in the communication interface module, and at least one serial interface integrated in the communication interface module can be used to configure the communication interface module.

Abstract: A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.

Abstract: A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.