Abstract: A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed.

Abstract: An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.

Abstract: An interface switching control method, a portable terminal and a portable mobile device using the method are disclosed. The method is applied in a portable terminal including a first device and a second device. The first device is connected to a shared device via a first interface, and the second device is connected to the shared device via a second interface. The portable terminal has a first state in which the first device and the second device are connected, and a second state in which the first device and the second device are disconnected. The method includes detecting a state of the portable terminal; and when the detection result indicates that the portable terminal is in the first state, controlling the first interface to be in an enabled state and controlling the second interface to be in a disabled state. The method achieves a real-time switching control over the interfaces for the shard device, and optimizes the interface control for the hybrid-system portable terminal.

Abstract: A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module supplies power to an output terminal. The at least one redundant power supply module operates in a first state and in a second state. In the first state the second power supply module supplies power to the output terminal. In the second state the second power supply module provides standby power and operates in a burst mode (for example, such as a discontinuous conduction mode).

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.

Abstract: An inhibition device includes: a location information obtaining section that obtains, from a computing device, information on a touch location; a operation determining section that determines, in accordance with the information on the touch location, whether or not an operation of a user is an operation for causing the computing device to execute a predetermined process; and an inhibition information transmitting section that transmits inhibition information.

Abstract: An electronic apparatus controls a peripheral device by using a relay apparatus. The electronic apparatus includes an interface connected to the peripheral device; a communication unit that performs communication with the relay apparatus; a receiver that receives a control signal for controlling the electronic apparatus; and a controller that, when the control signal is received, performs an operation based on the control signal, and controls the communication unit to transmit information about the performed operation and information about the peripheral device to the relay apparatus in order to control the peripheral device to perform an operation that corresponds to the performed operation.

Abstract: A sensor interface system includes a system bus, a bus master and a sensor. The bus master is coupled to the system bus. The bus master is configured to provide voltage regulation at a first band and perform data transmission within or at a second band. The sensor is also coupled to the system bus. The sensor is configured to receive or utilize the voltage regulation and to perform data transmission within or at the second band.

Abstract: An in-vehicle sensor (1) connected to a communication bus CAN includes a bus connection connector (40) including external communication terminals T3, T4, and external setting terminals T5, T6 each of which is brought into one of a plurality of connection states; judgment means S1-S7 for judging the connection states of the external terminals for setting T5, T6 when electric power is supplied in a state in which the bus connection connector (40) is connected to the communication bus CAN; identifier generation means S8 for generating an identifier ID of the in-vehicle sensor (1) based on the judged connection states; a nonvolatile storage section (11) for storing the identifier ID; communication means (10) for performing communications through the communication bus CAN using the stored identifier ID; and storing means S9 for storing a first generated initial identifier IDS in the storage section (11) as the identifier ID.

Abstract: A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information.

Abstract: The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state.

Abstract: A system and method can support message pre-processing in a distributed data grid. The system can associate a message bus with a service thread on a cluster member in the distributed data grid. Furthermore, the system can receive one or more incoming messages at the message bus using an input/output (I/O) thread, and pre-process said one or more incoming messages on the I/O thread before each said incoming message is delivered to a service thread in the distributed data grid. Additionally, the system can take advantage of a pool of input/output (I/O) threads to deserialize inbound messages before they are delivered to the addressed service, and can relieve the bottleneck that is caused by performing all message deserialization in a single threaded fashion before the message type can be identified and offloaded to the thread-pool within the distributed data grid.

Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Abstract: Provided are techniques for building an undo log for in-memory blocks of data. Permission on a block of data in memory is set to prevent updates to that block of data using a memory protection function. In response to an update operation attempting to update the block of data in the memory, an interrupt with a location of the block of data is received, the block of data is copied to an undo log entry in an undo log, and the permission on the block of data in the memory is set to allow the update to that block of data to proceed using the memory protection function.

Abstract: Provided are techniques for building an undo log for in-memory blocks of data. Permission on a block of data in memory is set to prevent updates to that block of data using a memory protection function. In response to an update operation attempting to update the block of data in the memory, an interrupt with a location of the block of data is received, the block of data is copied to an undo log entry in an undo log, and the permission on the block of data in the memory is set to allow the update to that block of data to proceed using the memory protection function.

Abstract: A system and method can a scalable message bus in a distributed data grid. The system can provide a plurality of message buses in the distributed data grid, wherein the distributed data grid includes a plurality of cluster members and provides a plurality of services. Furthermore, the system can associate each said service in the distributed data grid with a said message bus, and use the plurality of message buses to support data transferring between different services on different cluster members in the distributed data grid. Additionally, the system can use a datagram layer to support clustering in the distributed data grid, and bypass the datagram layer in the distributed data grid for data transferring.

Abstract: A sensor system utilizing adaptively selected carrier frequencies is disclosed. The system includes a system bus, a bus master, and a sensor. The system bus is configured to transfer power and data. The bus master is coupled to the system bus and is configured to provide power to the bus and receive data from the bus. The sensor is coupled to the system bus and is configured to transfer data on the bus using an adaptively selected carrier frequency.

Abstract: A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module supplies power to an output terminal. The at least one redundant power supply module operates in a first state and in a second state. In the first state the second power supply module supplies power to the output terminal. In the second state the second power supply module provides standby power and operates in a burst mode (for example, such as a discontinuous conduction mode).

Abstract: An electronic assembly including a first connector having a first set of terminals physically and operationally compliant with a data transmission connector standard, such as USB 2.0, and a second set of terminals distinct from the first set of terminals physically compliant and operationally non-compliant with this data transmission connector standard. An electronic controller is connected to the first connector. The controller includes a memory device to store configuration data, such as a battery charging profile, used by the controller to control a first electronic device, such as a battery charging device. The second set of terminals receive new configuration data to update the configuration data stored in the memory device. The assembly may include a specially configured data cable to interconnect the assembly to a separate electronic device to transmit the updated configuration data. The assembly may reduce the current supplied for battery charging by monitoring a battery voltage.

Abstract: In some embodiments, provided is a way for devices to request S0ix (or the like) entry and exit.