Abstract: An electronic device includes a transparent substrate, a number of pixel structures and a first trace structure. The transparent substrate includes a transparent region and a trace region. Each of the pixel structures has a sub-pixel structure of first color and a sub-pixel structure of second color. The sub-pixel structure of first color has a light emitting element of first color. The sub-pixel structure of second color has a light emitting element of second color. The first trace structure includes a first main trace, a first auxiliary trace and a second auxiliary trace. The first main trace is disposed in the trace region and surrounds a portion of the transparent region. The first auxiliary trace and the second auxiliary trace are electrically connected to the first main trace, and are electrically connected to the corresponding sub-pixel structure of first color and the corresponding sub-pixel structure of second color, respectively.

Abstract: A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.

Abstract: Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and a second color filter layer disposed adjacent to the first color filter layer, which respectively have a plurality of first color filter segments and a plurality of second color filter segments. Moreover, the solid-state image sensor includes a first metal grid structure disposed between the first color filter layer and the second color filter layer. The solid-state image sensor also includes a second metal grid structure disposed between the first color filter segments and between the second color filter segments. The bottom of the first metal grid structure has a first grid width, and the bottom of the second metal grid structure has a second grid width narrower than the first grid width.

Abstract: An organic light-emitting display device comprises a substrate; a plurality of sub-pixels arranged in a first horizontal line and a second horizontal line on the substrate; at least one thin film transistor and a first electrode of an organic light-emitting diode connected to the thin film transistor, the at least one thin film transistor and the organic light-emitting diode being disposed in each of the plurality of sub-pixels; a first bank layer is disposed on the first electrode and exposing the first electrode; and a second bank layer disposed on the first bank layer and exposing the first bank layer and the first electrode, wherein the second bank layer is consecutively arranged in the first horizontal line and the second horizontal line and including a first bending portion at a boundary between the first horizontal line and the second horizontal line.

Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposition inhibiting patterns, each deposition inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.

Abstract: A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.

Abstract: A recess is formed in one silicon substrate. A silicon oxide film is formed in another one silicon substrate at a portion space apart from a space-to-be-formed region. The silicon oxide film has a groove surrounding the space-to-be-formed region and extending to an outer periphery of the other one silicon substrate. Further, the other one silicon substrate and the one silicon substrate are directly bonded to each other via the silicon oxide film so as to cover the groove. A gas discharge passage, a stacking structure of the silicon substrates and the silicon oxide film are formed, and the space is formed inside the stacking structure by the recess. Then, by the heat treatment, the gas inside the space is discharged to the outside of the stacking structure through the gas discharge passage.

Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.

Abstract: A semiconductor package may include a line array of single-photon avalanche diodes (SPADs). The line array of single-photon avalanche diodes may be split between multiple silicon dice. The silicon dice may have a staggered arrangement, with prisms on the package lid redirecting incident light to the silicon dice. The silicon dice may alternate between a first side of the package substrate and a second side of the package substrate. The prisms may alternate between a first structure that redirects incident light to the first side of the package substrate and a second structure that redirects incident light to the second side of the package substrate. The silicon dice may overlap to allow satisfactory alignment between the silicon dice and the prisms.

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.

Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.

Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.

Abstract: Embodiments of die-to-die bonding schemes of three-dimensional (3D) memory devices are provided. In an example, a method for bonding includes dicing one or more device wafers to obtain a plurality of dies, placing at least one first die of the plurality of dies onto a first carrier wafer and at least one second die of the plurality of dies onto a second carrier wafer, and bonding the at least one first die each with a respective second die. The at least one first die and the at least one second die each are functional. In some embodiments, the method also includes removing, respectively, the first carrier wafer and the second carrier wafer to form a plurality of bonded semiconductor devices each having one of the first dies and the respective second die.

Abstract: A semiconductor device comprises a first semiconductor chip, a first planar waveguide transmission line arranged within a BEOL metal stack of the first semiconductor chip, wherein the first planar waveguide transmission line comprises line sections situated opposite one another, and a second planar waveguide transmission line arranged over the first semiconductor chip and electrically coupled to the first planar waveguide transmission line, wherein the second planar waveguide transmission line comprises line sections situated opposite one another.