Abstract: According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact and a first bonding alignment mark. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact and a second bonding alignment mark. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface.

Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.

Abstract: Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.

Abstract: A light emitting apparatus includes: a package substrate; a light emitting device housed in a recess of the package substrate; a window member provided to cover an opening of the recess; and a sealing structure that seals a space between the package substrate and the window member. The window member includes a glass plate having an inner surface that faces the optical semiconductor device and a frame body provided on the inner surface of the glass plate. The sealing structure includes a first metal layer provided on a top surface of the package substrate, a second metal layer provided on a bottom surface and an inner circumferential surface of the frame body, and a metal bonding part provided between the first and second metal layers, at least a portion of the metal bonding part being provided on the inner circumferential surface.

Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.

Abstract: Embodiments of the disclosed subject matter provide a device having a substrate, at least one organic light-emitting layer disposed over the substrate, and at least one down-conversion layer. The at least one down-conversion layer may generate the NIR emission by absorbing at least a portion of the light emitted by the at least one organic light emitting layer, and re-emitting light at a longer NIR wavelength or range of wavelengths having a peak NIR emission that may be greater than 700 nm, greater than 750 nm, or greater than 800 nm. An out-of-plane optical density of the at least one down-conversion layer may be less than 0.1 for all wavelengths of light in a range from 400 nm to 600 nm.

Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

Abstract: A method of a forming semiconductor fin structures that includes forming a plurality of fin structures with a first etch to a first depth in a substrate. The plurality of fin structures have a first width to the first depth. A spacer is formed on sidewalls of the plurality of fin structures. A second etch step can then extend the plurality of fin structures to a second depth with a second etch. The plurality of fin structures have a second width greater than the first width at the second depth portion. At least a portion of the trench separating adjacent fin structures may then be filled with a dielectric formed by an oxidation process. The portion of the fin structures extending above the dielectric fill is the active region of the fin structures which has a uniform height for all of the fin structure in the plurality of fin structures.

Abstract: A wafer processing method includes a protective member laying step of placing a protective member on a face side of a wafer, a reverse side grinding step of grinding a reverse side of the wafer to thin the wafer, a cut groove forming step of positioning a cutting blade in alignment with projected dicing lines one at a time on the reverse side of the wafer, cutting the wafer with the cutting blade to form cut grooves in the wafer which terminate short of the face side thereof, and a cutting step of applying a laser beam to the wafer from the reverse side thereof along the cut grooves to completely sever the wafer along the projected dicing lines into individual device chips.

Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.

Abstract: A Light Emitting Diode (LED) component includes a lead frame and an LED that is electrically connected to the lead frame without wire bonds, using a solder layer. The lead frame includes a metal anode pad, a metal cathode pad and a plastic cup. The LED die includes LED die anode and cathode contacts with a solder layer on them. The metal anode pad, metal cathode pad, plastic cup and/or the solder layer are configured to facilitate the direct die attach of the LED die to the lead frame without wire bonds. Related fabrication methods are also described.

Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

Abstract: Disclosed is an organic light emitting display device. The organic light emitting display device includes: at least one transistor arranged in a transistor region of the substrate and configured to include a channel layer, an insulation film, a gate electrode, a source electrode and a drain electrode; a storage capacitor arranged in the storage capacitor region, the pixel region and the pad region of the substrate and configured to include a first storage electrode, an insulation film pattern and a second storage electrode; a color filter arranged over the storage capacitor opposite to the pixel region; and an organic light emitting diode arranged on the color filter and configured to include a first electrode, an organic emission layer and a second electrode.

Abstract: Broadband signal transmissions may be used for object detection and/or ranging. Broadband transmissions may comprise a pseudo-random bit sequence or a bit sequence produced using, a random process. The sequence may be used to modulate transmissions of a given wave type. Various types of waves may be utilized, pressure, light, and radio waves. Waves reflected by objects within the sensing volume may be sampled. The received signal may be convolved with a time-reversed copy of the transmitted random sequence to produce a correlogram. The correlogram may be analyzed to determine range to objects. The analysis may comprise determination of one or more peaks/troughs in the correlogram. Range to an object may be determines based on a time lag of a respective peak.

Abstract: A method of forming a semiconductor structure includes forming two or more catalyst nanoparticles from a metal layer disposed over a substrate in two or more openings of a hard mask patterned over the metal layer. The method also includes growing two or more carbon nanotubes using the catalyst nanoparticles, and removing the carbon nanotubes to form two or more nanoscale pores. The two or more nanoscale pores may be circular nanoscale pores having a substantially uniform diameter. The two or more openings in the hard mask may have non-uniform size, and the substantially uniform diameter of the two or more nanopores may be controlled by a size of the carbon nanotubes.

Abstract: An analysis system includes a storage module for storing a track indicating in time series a position of an individual that is moving as track data and for storing sensor data indicating in time series a measurement result of the individual by a sensor worn by the individual, a speed calculation module for calculating a speed index indicating a movement speed of the individual based on the track data, an index calculation module for calculating a behavior index indicating a movement intensity of the individual based on the sensor data, a similarity degree calculation module for calculating a degree of similarity between the speed index and the behavior index based on changes in time series of the speed index and the behavior index, and an association module for associating the track and the individual on which the sensor data has been measured based on the degree of similarity.