Patents Examined by Brook Kebede
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Patent number: 10056344Abstract: A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed and a second area in which a plurality of second connecting portions are disposed. A second surface of a second substrate included in the semiconductor device includes a third area in which the plurality of first connecting portions are disposed and a fourth area in which the plurality of second connecting portions are disposed. The second area surrounds the first area on the first surface. The fourth area surrounds the third area on the second surface. A height of the second base electrode in a thickness direction of the first substrate is greater than a height of the first base electrode in the thickness direction.Type: GrantFiled: October 25, 2017Date of Patent: August 21, 2018Assignee: OLYMPUS CORPORATIONInventor: Haruhisa Saito
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Patent number: 10056481Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.Type: GrantFiled: January 13, 2017Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Christian Schippel, Andrei Sidelnicov, Gerd Zschaetzsch
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Patent number: 10049886Abstract: A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical.Type: GrantFiled: October 30, 2014Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hung Lin, Sheng-Shin Lin, Ying-Chieh Hung, Yu-Ting Huang, Tze-Liang Lee
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Patent number: 10050019Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.Type: GrantFiled: January 13, 2017Date of Patent: August 14, 2018Assignee: SK hynix Inc.Inventors: Tae Hoon Kim, Jong Hoon Kim, Dae Won Kim, Hyeong Seok Choi
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Patent number: 10049848Abstract: Technologies are described for methods for fabricating a film component. The methods may comprise sputtering a first film onto a substrate. The first film may include a semiconductor compound material. The semiconductor compound material may include a semi-metal material and one or more alkali material. The methods may further comprise evaporating a second film onto the first film. The second film may include the one or more alkali materials. The one or more alkali materials may catalyze crystallization of the semiconductor compound material in the first film substantially throughout the first film to form the film component in the first layer.Type: GrantFiled: June 10, 2016Date of Patent: August 14, 2018Assignees: Brookhaven Science Associates, LLC, The Regents of the University of CaliforniaInventors: John Smedley, Klaus Attenkofer, Susanne Schubert, Mengjia Gaowei, John Walsh
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Patent number: 10049924Abstract: Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.Type: GrantFiled: May 31, 2017Date of Patent: August 14, 2018Assignee: ASM INTERNATIONAL N.V.Inventors: Suvi P. Haukka, Antti Niskanen, Marko Tuominen
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Patent number: 10050142Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: October 20, 2017Date of Patent: August 14, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Patent number: 10037963Abstract: A package structure and method of forming the same includes: a first package including: a first die; a via adjacent the first die; a molding compound encapsulating the via and at least laterally encapsulating the first die around a perimeter of the first die; and a first redistribution structure extending over the first die and the molding compound; a first integrated passive device (IPD) attached to the first redistribution structure, the first IPD disposed proximate the perimeter of the first die; a second IPD attached to the first redistribution structure, the second IPD disposed distal the perimeter of the first die; and an underfill disposed between the first IPD and the first redistribution structure, the second IPD being free of the underfill.Type: GrantFiled: March 3, 2017Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jie Chen, Chen-Hua Yu, Hsien-Wei Chen, Der-Chyang Yeh
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Patent number: 10037957Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.Type: GrantFiled: November 14, 2016Date of Patent: July 31, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
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Patent number: 10032812Abstract: A method is presented for fabricating an array of sensors on an object having a non-developable surface. The method includes: growing an epitaxial structure on a substrate; bonding, without the use of an adhesive, the epitaxial structure to a flexible membrane to form a device structure; forming an array of sensors from the epitaxial structure of the device structure using photolithographic techniques; cutting the device structure into segments; and bonding the segments onto the target object.Type: GrantFiled: January 6, 2017Date of Patent: July 24, 2018Assignee: The Regents of The University of MichiganInventors: Stephen R. Forrest, Kyusang Lee
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Patent number: 10026642Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a sacrificial layer.Type: GrantFiled: March 6, 2017Date of Patent: July 17, 2018Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventor: Sasha Joseph Kweskin
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Patent number: 10026887Abstract: In some aspects, the present disclosure provides methods of depositing a metal onto a nanomaterial which has been passivized with a self-assembled monolayer at a weakened point in the topography of the nanomaterial. In some embodiments, the weakened point is caused by the curvature of the topography. This method may be used to prepare electronic devices such as memory modules.Type: GrantFiled: November 14, 2016Date of Patent: July 17, 2018Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: John G. Ekerdt, Sonali N. Chopra
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Patent number: 10020260Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.Type: GrantFiled: December 22, 2016Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shafaat Ahmed, Benjamin G. Moser, Vimal Kumar Kamineni, Dinesh Koli, Vishal Chhabra
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Patent number: 10014201Abstract: Systems and methods are described for transferring wafers between processing steps in the fabrication of solar cells. The wafers may be processed using a cluster tool including a load-lock, a plurality of processing modules, and a central robot to transfer wafers between the plurality of modules. Each module may include a pedestal including wafer recesses to support the wafers, and puck recesses for supporting ferromagnetic pucks below the wafers. The central robot includes electromagnets for attracting the ferromagnetic pucks toward the electro magnets in order to clamp the wafers between the ferromagnetic pucks and the electromagnets.Type: GrantFiled: December 16, 2016Date of Patent: July 3, 2018Assignee: SolarCity CorporationInventor: Edward Sung
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Patent number: 10014461Abstract: A method is provided for producing an electrically-powered device and/or component that is embeddable in a solid structural component, and a system, a produced device and/or a produced component is provided. The produced electrically powered device includes an attached autonomous electrical power source in a form of a unique, environmentally-friendly structure configured to transform thermal energy at any temperature above absolute zero to an electric potential without any external stimulus including physical movement or deformation energy. The autonomous electrical power source component provides a mechanism for generating renewable energy as primary power for the electrically-powered device and/or component once an integrated structure including the device and/or component is deployed in an environment that restricts future access to the electrical power source for servicing, recharge, replacement, replenishment or the like.Type: GrantFiled: February 12, 2018Date of Patent: July 3, 2018Assignee: Face International CorporationInventors: Clark D Boyd, Bradbury R Face, Jeffrey D Shepard
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Patent number: 10008507Abstract: Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.Type: GrantFiled: April 14, 2016Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang
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Patent number: 10003170Abstract: A soldering system that determines soldering quality of elements relative to a housing at the moment of soldering semiconductor laser elements. A soldering device that performs soldering of a semiconductor laser element to a semiconductor laser module, a robot that conveys the module, a camera, and a control device that controls the robot and camera based on imaging output of the camera. The robot conveys the module and changes the position and posture of the camera. The camera images the module. The control device calculates the position of the semiconductor laser element based on the imaging output, calculates parallelism between the housing of the module and the semiconductor laser element based on the change in light intensity related to the imaging output when changing the relative position between the camera and the subject, and determines the quality of soldering of the semiconductor laser element based on the position and parallelism.Type: GrantFiled: June 6, 2017Date of Patent: June 19, 2018Assignee: FANUC CORPORATIONInventor: Tetsuhisa Takazane
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Patent number: 9997408Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.Type: GrantFiled: October 1, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Terry A. Spooner
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Patent number: 9997562Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.Type: GrantFiled: March 14, 2017Date of Patent: June 12, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lei Wang, Benfu Lin, Chim Seng Seet, Kai Hung Alex See
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Patent number: 9997447Abstract: A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.Type: GrantFiled: June 8, 2017Date of Patent: June 12, 2018Assignee: ADVANCED SSEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Hung-Yi Lin, Sheng-Chi Hsieh