Abstract: There is provided an imaging device manufacturing method contributing to improved reliability and yield. The method includes forming a first insulating film on a polysilicon film and then removing a portion of the first insulating film formed on a second main surface and a portion of the first insulating film formed on a side surface of the substrate to expose a polysilicon film. After the polysilicon film is exposed, a second insulating film is formed on the first main surface by a plasma chemical vapor deposition (CVD) method.

Abstract: A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electrical characteristics, is provided. A semiconductor device is provided with a transistor that includes an oxide semiconductor film, a gate electrode overlapping with part of the oxide semiconductor film, and a gate insulating film between the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a first region and second regions between which the first region is positioned. The second regions include an impurity element. A side of the gate insulating film has a depressed region. Part of the gate electrode overlaps with parts of the second regions in the oxide semiconductor film.

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET includes source and drain electrodes on opposite sides of the fin. The FET also includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions extending completely from a surface of the second channel region facing the first channel region to a surface of the first channel region facing the second channel region. The FET includes a gate stack extending along a pair of sidewalls of the stack. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions.

Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

Abstract: A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region.

Abstract: A photovoltaic (PV) Module can include a substantially transparent cover, first encapsulant, a solar cell and a second encapsulant. The second encapsulant can be configured to allow thermal communication between the solar cell and a heat sink. Various configurations and methods of making the same are presented.

Abstract: A display device including a substrate, a display unit on the substrate and including a display element for displaying an image, at least one organic encapsulation film formed on the display unit, and at least one refractive-index control encapsulation film adjacent to the at least one organic encapsulation film. A refractive index of a region of the at least one refractive-index control encapsulation film closer to the at least one organic encapsulation film is closer to a refractive index of the at least one organic encapsulation film than is a refractive index of a region of the at least one refractive-index control encapsulation film further from the at least one organic encapsulation film.

Abstract: Photodiodes and nuclear batteries may utilize actinide oxides, such a uranium oxide. An actinide oxide photodiode may include a first actinide oxide layer and a second actinide oxide layer deposited on the first actinide oxide layer. The first actinide oxide layer may be n-doped or p-doped. The second actinide oxide layer may be p-doped when the first actinide oxide layer is n-doped, and the second actinide oxide layer may be n-doped when the first actinide oxide layer is p-doped. The first actinide oxide layer and the second actinide oxide layer may form a p/n junction therebetween. Photodiodes including actinide oxides are better light absorbers, can be used in thinner films, and are more thermally stable than silicon, germanium, and gallium arsenide.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A conductive element protrudes from the upper surface of the floating gate conductor into an opening. A dielectric material defines a reaction region. The reaction region overlies and extends below an upper surface of the conductive element.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A PZT precursor solution is used for forming a PZT film by a sol-gel method. The PZT precursor solution includes a solvent; a component that forms a crystal of PZT by crystallization, the component being dissolved in the solvent; and an element that inhibits crystal growth of PZT, the element being dissolved in the solvent.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract: An oxide semiconductor film having high stability with respect to light irradiation or a semiconductor device having high stability with respect to light irradiation is provided. One embodiment of the present invention is a semiconductor film including an oxide in which light absorption is observed by a constant photocurrent method (CPM) in a wavelength range of 400 nm to 800 nm, and in which an absorption coefficient of a defect level, which is obtained by removing light absorption due to a band tail from the light absorption, is lower than or equal to 5×10?2/cm. Alternatively, a semiconductor device is manufactured using the semiconductor film.

Abstract: Nano-electromechanical systems (NEMS) devices that utilize thin electrically conductive membranes, which can be, for example, graphene membranes. The membrane-based NEMS devices can be used as sensors, electrical relays, adjustable angle mirror devices, variable impedance devices, and devices performing other functions.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.

Abstract: Methods for fabricating radiation-detecting structures are presented. The methods include, for instance: fabricating a radiation-detecting structure, the fabricating including: providing a semiconductor substrate, the semiconductor substrate having a plurality of cavities extending into the semiconductor substrate from a surface thereof; and electrophoretically depositing radiation-detecting particles of a radiation-detecting material into the plurality of cavities extending into the semiconductor substrate, where the electrophoretically depositing fills the plurality of cavities with the radiation-detecting particles. In one embodiment, the providing can include electrochemically etching the semiconductor substrate to form the plurality of cavities extending into the semiconductor substrate.

Abstract: In various embodiments, an optoelectronic component is provided. The optoelectronic component includes a carrier body. An optoelectronic layer structure is formed above the carrier body and has at least one contact region for electrically contacting the optoelectronic layer structure. A covering body is arranged above the optoelectronic layer structure. At least one contact cutout in which at least one part of the contact region is exposed extends through the carrier body and/or the covering body. At least one plug element for electrically contacting the optoelectronic component is arranged at least partly in the contact cutout and tightly closes the contact cutout. A contact medium, via which the plug element is electrically coupled to the contact region, is arranged in the contact cutout.

Abstract: A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening.

Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.