Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: A method of manufacturing a light emitting device includes: providing a light emitting device set that includes a lead frame being plate-like and including pairs of supporting leads each of which pairs consists of a first supporting lead and a second supporting lead, packages respectively supported by the pairs of supporting leads, and light emitting elements respectively mounted on the packages; and removing the packages from the lead frame. The packages each include a resin molded body, the resin molded body includes a first recess open at the first and third outer surfaces, and a second recess open at the second and third outer surfaces. The first supporting lead and the second supporting lead respectively fit into the first recess and the second recess. In the removing step, the packages are each removed from the lead frame by the third outer surface being pushed.

Abstract: Methods and apparatuses for forming high modulus silicon oxide spacers using atomic layer deposition are provided. Methods involve depositing at high temperature, using high plasma energy, and post-treating deposited silicon oxide using ultraviolet radiation. Such silicon oxide spacers are suitable for use as masks in multiple patterning applications to prevent pitch walking.

Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

Abstract: The present disclosure provides a light-emitting device, comprising: a light-emitting stack; a first semiconductor layer on the light-emitting stack; a first electrode formed on the first semiconductor layer and comprising an inner segment, an outer segment, and a plurality of extending segments electrically connecting the inner segment with the outer segment.

Abstract: An organic EL display panel manufacturing method including: preparing a substrate; forming at least first electrodes on the substrate; forming, by performing photolithography on the substrate having the first electrodes, a bank layer made of a photoresist and having apertures corresponding one-to-one with the first electrodes; forming a functional layer in each of the apertures by applying an ink containing a functional material to the aperture and drying the applied ink; and forming at least a second electrode on the functional layer. The forming of the bank layer includes: applying the photoresist to the substrate having the first electrodes; forming apertures corresponding one-to-one with the first electrodes in the photoresist by performing exposure using a mask and then developing the photoresist; after forming the apertures, performing exposure of the photoresist having the apertures; after performing the exposure of the photoresist having the apertures, baking the photoresist.

Abstract: An embodiment includes an apparatus comprising: a substrate; a first die including a processor core; a second die not including a processor core; and a third die including memory cells; wherein: (a)(i) the first die has a smaller minimum pitch than the second die; (a)(ii) a first vertical axis intersects the substrate and the first and second dies but not the third die; and (a)(iii) a second vertical axis intersects the substrate and the second and third dies but not the first die. Other embodiments are described herein.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of tip-to-side shorts and/or leakages.

Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.

Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

Abstract: A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a base substrate, a first TFT having a polycrystalline semiconductor and disposed on the base substrate, and a second TFT having an oxide semiconductor and disposed on the first TFT. The second TFT overlaps at least a portion of the first TFT in a plan view.

Abstract: The invention presents an intelligent deployment cascade control (IDCC) device for frequency division duplexing (FDD)-orthogonal frequency division multiplexing access (OFDMA) indoor small cell to enable easy installation, multi-user (MU)service reliability, optimum throughput, power saving, minimum interference and good cell coverage. The proposed IDCC device is designed with a cascade architecture, which mainly contains five units including a resource allocator, a minimum throughput/cell edge CQI converter, an adaptive neural fuzzy inference system (ANFIS) based initial transmit power setting controller (ITPSC) in the first cascade unit, an ANFIS based channel quality index (CQI) decision controller (CQIDC) in the second cascade unit and an ANFIS based self-optimization power controller (SOPC) in the third cascade unit. The SOPC consists of three parts, namely the transmit power adjustment estimator (TPAE), transmission power assignment and self-optimization power controller protection mechanism.

Abstract: The present invention relates to a method for the production of at least one three-dimensional layer of solid material, in particular for usage as wafer, and/or at least one tree-dimensional solid body.

Abstract: A gate dielectric layer and a gate electrode layer are formed around semiconductor pillars. The gate electrode layer is patterned to remove top portions that protrude above the semiconductor pillars and divided into multiple strips. Each strip constitutes a gate electrode line including a horizontal layer portion and a plurality of surrounding portions that entirely laterally surround respective channel regions of the semiconductor pillars to form wrap gate vertical select field effect transistors. Vertical stacks of memory elements and alternating layer stacks including a vertically alternating sequence of insulating strips and electrically conductive word line strips are formed above the vertical field effect transistors. Vertical bit lines can be formed inside the vertical stacks of memory elements.

Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A sensing pixel array used in an image sensor includes sensing pixel units each including a photodiode, a row reset transistor, a buffer transistor, and a column control transistor at least. Photodiode converts light into a sensing signal. Row reset transistor is coupled to a reference reset signal and photodiode, and is controlled by a row reset signal. Buffer transistor is coupled to the output of photodiode to receive and buffer the sensing signal. Column control transistor is electrically connected to the control end or the output of the buffer transistor and is used as a switch which can be closed or open according to a column control signal to control whether to transfer charge of the reference reset signal to a capacitor when the row reset transistor becomes conductive.

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuitry may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.