Abstract: A computer system and method for synchronizing actions associated with media between a media/network device and peripherals. In an example implementation, a system includes a one or more processors configured to receive, by a communication module from a media/network device based on peripheral addressing information, a peripheral payload including a first set of actions and timing information related to media. The one or more processors perform the first set of actions based on the peripheral payload, generate response data for the first set of actions, and transmit the response data to the media/network device via a wireless network.

Abstract: The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: A computer system includes symmetrical sets of motherboard serial channels which couple processor devices on a motherboard with a common serial link interface. The common serial link interface can be coupled with an endpoint device to establish symmetrical serial links between the endpoint device and the processor devices. The computer system can include a riser card which can be coupled with the serial link interface. The riser card can include an endpoint device interface and serial channels which can couple the processor devices with the endpoint device via symmetrical limited selections of the motherboard serial channels. The riser can include additional interfaces which can couple the processor devices with additional expansion devices.

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Abstract: A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.

Abstract: An I/O interface configuration device for configuring I/O interfaces comprises an input interface, an output interface, a storage unit, a detecting pin, a converting unit and a computing unit. The input interface electrically connects to a controlling port of a controlling circuit to receive a data type. The output interface electrically connects to a controlled port of a controlled device to output another data type. The storage unit stores a plurality of configuration files, one of the configuration files corresponds to a circuit type of the controlling circuit. The detecting pin is adapted to retrieve the circuit type. The converting unit converts the data type to said another data type and selectively outputs said another data type from the output interface. The computing unit loads the configuration file corresponding to the circuit type and control the converting unit to configure the I/O interface according to the configuration file.

Abstract: Presented herein are methods, non-transitory computer readable media, and devices for selectively limiting the amount of data in a file system, which include: determining a reparity bit value for a write disk block range, wherein the reparity bit is configured to track a number of writes in progress to a stripe range; determining the reparity bit value; updating a threshold written disk block number as a highest disk block number of the reparity bit value; and initiating a RAID operation until it reaches the threshold written disk block number, wherein the threshold written disk block number comprises a maximum written disk block number representing the last disk block number written.

Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.

Abstract: A technique is directed to performing a tuning operation in data storage equipment. The technique involves generating, while the data storage equipment performs input/output (I/O) transactions, an observed I/O statistics profile based on performance of at least some of the I/O transactions. The technique further involves performing a comparison operation that compares the observed I/O statistics profile to an expected I/O statistics profile which is defined by a set of operating settings that controls operation of the data storage equipment. The technique further involves operating the data storage equipment in a normal state when a result of the comparison operation indicates that the observed I/O statistics profile matches the expected I/O statistics profile and in a remedial state which is different from the normal state when the result of the comparison operation indicates that the observed I/O statistics profile does not match the expected I/O statistics profile.

Abstract: During a memory reallocation process, it is determined that a set of memory pages being reallocated are each enabled for a Direct Memory Access (DMA) operation. Prior to writing initial data to the set of memory pages, a pre-access delay is performed concurrently for each memory page in the set of memory pages.

Abstract: A method for handling an interrupt includes receiving, in hardware or in firmware, a request from a task executing in userspace, where the request is to assign a function in the task and state information for the task to an interrupt. The hardware or firmware records the state information for the task, and assigns defined state information for the function to an event caused by the interrupt. When the interrupt occurs, the interrupt is serviced by saving context including the state information for the task in the memory, loading the defined state information for the function into registers, running the function, and then returning to the task preempted by the interrupt.

Abstract: An extension apparatus for a universal serial bus (USB) interface includes a transmitting device, a receiving device and an electrical signal network cable. The transmitting device includes the following elements: a first packet-processing unit to receive a first interface packet and generate an original data accordingly, a first buffering unit to temporarily store the original data, and a first data-converting unit to generate and output a network packet signal based on the original data. The receiving device includes the following elements: a second data-converting unit to receive the network packet signal and generate the original data accordingly, a second buffering unit to temporarily store the original data, and a second packet-processing unit to receive the original data and generate the first interface packet. The electrical signal network cable is electrically coupled between the transmitting device and the receiving device to transmit the network packet signal.

Abstract: A storage system is provided. The storage system includes a backplane; a plurality of single port storage devices; and a plurality of controllers, wherein the backplane routes a plurality of interconnection lanes between the plurality of controllers and the plurality of single port storage devices, wherein the plurality of controllers is configured to: enable at least one second interconnection lane of the plurality of interconnection lanes when a first controller of the plurality of controllers has failed, wherein a first interconnection lane of the plurality of interconnection lanes is between the first controller and a first single port storage device of the plurality of single port storage devices, wherein the at least one second interconnection lane is between a second controller of the plurality of controllers and the first single port storage device.

Abstract: Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A computer system and method for synchronizing actions associated with media between a media/network device and peripherals. In an example implementation, a system includes a one or more processors configured to receive, by a communication module from a media/network device based on peripheral addressing information, a peripheral payload including a first set of actions and timing information related to media. The one or more processors perform the first set of actions based on the peripheral payload, generate response data for the first set of actions, and transmit the response data to the media/network device via a wireless network.

Abstract: A semiconductor apparatus may include a command receiving circuit, a multiplexing circuit, and a DQ circuit. The command receiving circuit may be configured to latch signal bits of a command according to a clock signal, and output the latched signal bits as latched signals. The multiplexing circuit may be configured to receive the latched signals from the command receiving circuit, and selectively output the latched signals according to a flag signal which is internally generated within the semiconductor apparatus. The DQ circuit may be configured to receive the selectively outputted latched signals from the multiplexing circuit and receive the flag signal, and configured to output the selectively outputted latched signals and the flag signal as a feedback command to the outside of the semiconductor apparatus through a plurality of DQ pins.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.