Abstract: A memory control device of the present invention controls a memory that includes multiple bank groups each including multiple banks. The memory control device includes a request buffer configured to store memory requests to be issued to the banks, a bank busy manager configured to manage busy states of the banks, a bank group checker configured to, for each of the banks, manage the number of banks in not-busy state of the banks in each of the bank groups, a bank group determination unit configured to determine a bank group to which a memory request is issued, on the basis of the numbers of the banks in not-busy state in the respective bank groups, and a request issuer configured to issue the memory request in the request buffer to a bank in the determined bank group.

Abstract: A method for dynamically adjusting utilization of I/O processing techniques includes providing functionality to execute a plurality of I/O processing techniques. The I/O processing techniques include a first I/O processing technique that uses a higher performance communication path for transmitting I/O and a second I/O processing technique that uses a lower performance communication path for transmitting I/O. The method automatically increases use of the first I/O processing technique and reduces use of the second I/O processing technique when the set of conditions is satisfied. Similarly, the method automatically increases use of the second I/O processing technique and reduces use of the first I/O processing technique when the set of conditions is not satisfied. A corresponding system and computer program product are also disclosed.

Abstract: A rack-mountable data storage system includes: a chassis including one or more switchboards; a midplane interfacing with the one or more switchboards; and one or more data storage devices removably coupled to the midplane using a connector. At least one data storage device of the one or more data storage devices include a logic device to interface with the midplane. The logic device provides a device-specific interface of a corresponding data storage device with the midplane. The at least one data storage device is configured using the logic device according to a first protocol based on a signal on a pin of the connector, and the at least one data storage device is reconfigurable according to a second protocol based on a change of the signal on the pin of the connector using the logic device.

Abstract: Cache hits are increased for URBs that target a redirected USB device. When a virtual bus driver in a VDI environment queues an IRP for an URB that targets the redirected USB device, it can ensure that the IRP and therefore the URB is completed on the same processor that originated the URB. This can be accomplished in both NUMA and non-NUMA multiprocessor environments.

Abstract: The invention introduces a method for uninstalling SSD (Solid-state Disk) cards, performed by a processing unit when loading and executing a driver, including at least the following steps: reading the value of the register of an SSD card on which there is an access attempt according to a data access command in the time period between reception of the data access command from an application and transmission of a data access request corresponding to the data access command to lower layers; and executing an uninstall procedure when detecting that the SSD card has been removed according to a result of the reading.

Abstract: A system includes a rack with multiple hardware acceleration devices and at least one modular controller coupled together into one or more particular processing systems. Each modular hardware acceleration device includes multiple hardware accelerators, such as graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other specialized processing circuits. In each modular hardware acceleration device, the multiple hardware accelerators are communicatively coupled to a multi-port connection device, such as a switch, that is also communicatively coupled to at least two external ports of the modular hardware acceleration device. A modular controller of a particular processing system coordinates operation of hardware accelerators of multiple hardware acceleration devices included in the particular processing system to provide advanced processing capabilities.

Abstract: Systems and methods for protocol-tolerant communications in a Controller Area Network (CAN) are described. In some embodiments, a method may include receiving a frame at a network node; identifying, by the network node, a bit in a selected field of the frame; and determining, by the network node, that the frame follows a second format despite the bit indicating that the frame follows a first format. In other embodiments, a CAN controller includes message processing circuitry; and a memory coupled to the message processing circuitry, the memory having program instructions that configure the message processing circuit to: receive a frame; identify a bit in a selected field of the frame; and determine that the frame follows a Classical CAN format despite the bit indicating that the frame follows a flexible data-rate CAN (CAN FD) format.

Abstract: An apparatus includes a host and a baseboard. An out-of-band request is received via a host network interface of the host. The baseboard includes a management controller operating independently of the host and coupled to a management network interface separate from the host network interface. The out-of-band request is sent via an in-band communications channel from a proxy server of the host to a management agent running on the management controller microprocessor. Management data is formatted via the management agent. The management data is sent to the proxy server via the in-band communications channel. The management data describes hardware status that is obtained via the management controller in response to the out-of-band request. The management data is sent from the host network interface in response to the out-of-band request.

Abstract: A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.

Abstract: A bridge device tracks each individual IO between two PCIe busses and provides a translated address based on a scatter/gather list. Tracking provides a natural means of scatter/gather list translation to and from a native PCIe storage protocol's scatter/gather list (or other scatter/gather like mechanism). In addition, the awareness of the IO context provides a means for detecting erroneous transactions that would otherwise cause a system error and/or data corruption to be aborted preventing those error scenarios.

Abstract: An information handling system receives power from plural power sources by managing bi-directional power transfer at plural cable ports to maintain matched impedance across plural power sources. A power manager of an information handling system exchanges power characteristics with the plural power sources to coordinate power transfer in proportion to current capability of the power sources so that voltage droop at the different external power sources remains the same during variable power draws.

Abstract: An electronic device includes a memory; a communication interface; and a processor configured to: based on a source device connected through the communication interface being identified to support a version of content transmission encryption, change first Extended Display Identification Data (EDID) information stored in the memory to second EDID information; and change a hot plug detect signal related to the communication interface from a low state to a high state.

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract: The invention relates to an electronic circuit for interconnecting a smartcard chip with a peripheral device, comprising: —a dedicated communication interface adapted to communicate with a smartcard chip; —a configurable communication interface adapted to communicate with a peripheral device; —a configuration module adapted to receive on said dedicated communication interface a request for configuring the configurable communication interface, adapted to configure the communication protocol of the configurable communication interface with the peripheral device based on the received request; —a bridging module adapted for converting data exchanged between the peripheral device and the smartcard chip through the dedicated communication interface and the configurable communication interface.

Abstract: An intelligent platform integrates with an intelligent portable device or intelligent core to provide a dynamic computer that may serve as any of: a pad, a tablet computing device, a netbook computer, and a notebook computer. The operations of the integrated device are determined by the connected intelligent core's CPU architecture and its installed operating system. The intelligent platform includes a housing and a core slot located behind a display for accommodating the intelligent core. A core connector is provided on an inner wall of the core slot for interconnecting with a compatible connector of the inserted intelligent core. A control unit continually communicates with the intelligent core through signals carried by the connector, refreshes image received from the intelligent core on its touch-sensitive display, and sends touch-input commands from the touchable panel of the touch-sensitive display to the intelligent core.

Abstract: A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a direct memory access controller (DMAC). In one embodiment, the method includes calling a function stored in the flash memory, wherein a first parameter is passed to the function when it is called, wherein the first parameter identifies a first data structure that is stored in flash memory, and wherein the first data structure includes first DMAC control values. The CPU reads the first DMAC control values in response to the CPU executing instructions of the function. The CPU then writes the first DMAC control values to respective control registers of the DMAC in response to the CPU executing instructions of the function.

Abstract: A method and system for determining interface compatibility between components are provided. In the system for determining interface compatibility in component model-based software design, the system includes a compatibility rule manager managing interface compatibility rules, and an interface compatibility validator verifying interface compatibility between components based on the interface compatibility rules.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: A rack-mountable data storage system includes: a chassis including one or more switchboards; a midplane interfacing with the one or more switchboards; and one or more data storage devices removably coupled to the midplane using a connector. At least one data storage device of the one or more data storage devices include a logic device to interface with the midplane. The logic device provides a device-specific interface of a corresponding data storage device with the midplane. The at least one data storage device is configured using the logic device according to a first protocol based on a signal on a pin of the connector, and the at least one data storage device is reconfigurable according to a second protocol based on a change of the signal on the pin of the connector using the logic device.

Abstract: Disclosed herein is a processing system, including: a GPU generating a video; a memory storing data; a data bus connecting the GPU and the memory to each other; a DMA controller connected to the data bus; an input/output bridge connected to the data bus and connected to an external bus for transferring data to and from an external processing system which cooperates with the processing system; and a CPU cooperating with the GPU to share the data stored in the memory. The GPU issues a data transfer instruction of the data stored in the memory to the DMA controller without intervention of the CPU. The DMA controller controls, when the data transfer instruction is received, the input/output bridge to transfer the data stored in the memory to the external processing system.