Abstract: A memory device controlling apparatus of the present invention includes a device information requesting part that requests device information with respect to a memory device, when recognizing that the memory device is connected to the memory device controlling apparatus, and an extension activating part that activates an extension of the memory device based on the device information acquired in the device information requesting part. The memory device controlling apparatus accesses the memory device using the extension in the memory device. Such a configuration enables the memory device and the memory device controlling apparatus to be operated in an optimum operation mode in accordance with the characteristics of each bus, a host PC, and the memory device.

Abstract: Dynamic data partitioning for stateless request routing may be implemented. Respective partitions of data and corresponding mapping information may be maintained at partition hosts. A repartitioning event may be detected for the data to move a portion of data from a source partition host to a destination partition host. In response, the mapping information at the source partition host may be updated to indicate that the portion of data is located at the destination partition host for subsequent access requests received at the source partition host. The portion of the data may be copied from the source partition host to the destination partition host. Upon completion of the copy of the portion of the data, the mapping information at the destination partition host may be updated to indicate that the portion of the data is located at the destination partition host and is available for access.

Abstract: A method of controlling a terminal is provided. The method includes determining a current status of at least one of the terminal and a peripheral environment of the terminal based on information obtained by using at least one sensor from a predetermined list of a plurality of statuses regarding the terminal or the peripheral environment of the terminal, determining an operation schedule of the at least one sensor based on the determined current status and the information obtained by using the at least one sensor, and controlling the at least one sensor to operate based on the determined operation schedule.

Abstract: Described herein are methods, systems and machine-readable media that facilitate an analysis of the contributing factors of storage system latency. The variation over time of the storage system latency is measured, along with the variation over time of the activity of various processes and/or components, the various processes and/or components being potentially contributing factors to the storage system latency. The latency measurements are correlated with the process and/or component measurements. High correlation, while not providing direct evidence of the causation of latency, is nevertheless used to identify likely factors (i.e., processes, components) contributing to latency. The latency measurements are plotted over time, the plot including supplemental information indicating, at any time instant, likely factors contributing to the storage system latency.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: A method for communications includes receiving in a network interface controller (NIC) of a host computer incoming data packets from a network on multiple active rings. An average throughput rate of the incoming data packets is measured over the active rings. For each ring among a plurality of the active rings, a respective throughput rate of the incoming data packets on the ring is measured, and a respective interrupt moderation parameter of the ring is set responsively to a comparison of the respective throughput rate on the ring to the average throughput rate. Interrupts are issued from the NIC to a central processing unit (CPU) of the host computer in response to the incoming data packets on the ring at a rate determined in accordance with the respective interrupt moderation parameter.

Abstract: An information handling system receives power from plural power sources by managing bi-directional power transfer at plural cable ports to maintain matched impedance across plural power sources. A power manager of an information handling system exchanges power characteristics with the plural power sources to coordinate power transfer in proportion to current capability of the power sources so that voltage droop at the different external power sources remains the same during variable power draws.

Abstract: An extension point virtualization system uses operating system-provided reparse points to provide minimal extension point registration. Reparse points preserve application isolation while removing the scale problem of writing custom extension point proxies for each extension point. Instead, the system can use a single file system filter that generically handles application virtualization reparse points, and store reparse point data for extension points that need redirection. Many extension points can be handled by redirecting the operating system from a typical location for an application resource to a virtualized safe location for the application resource. Thus, the system simplifies the process of handling new extension points by allowing an application virtualization system to simply register new locations that should be handled with reparse points and to then handle registered locations generically.

Abstract: A method and system defines a mechanism to architect and define extensible methods and processes to build hybrid solutions. Solution templates provide a mechanism to architect and define the software development method in an extensible way and it enables the method architecture to be flexible to assemble method content and process elements only for those solution types that are necessary for a given solution. Solution templates keep the common base method lightweight and reusable and control the proliferation of software development processes necessary to build hybrid solutions by defining the solution templates for each of the solution types as pluggable extensions or add-ons to the base method that can be assembled on demand based on project needs.

Abstract: Transferring data to an initiator includes providing a first target that exchanges commands and status with the initiator, providing a second target that exchanges commands and data with the first target and exchanges data with the initiator, the initiator providing a transfer command to the first target, the first target providing a transfer command to the second target, and in response to the transfer command received from the first target, the second target transferring data to the initiator. Data may be transferred to the initiator using RDMA. The second target may provide a status message to the first target indicating a result of transferring data. The first target may provide the status message to the initiator. The first target may be a host adaptor of a data storage array. The second target may be a flash memory. The initiator may be a host coupled to the data storage array.

Abstract: Provided is an analog input and output module, the module comprising a first signal processing unit configured to separate analog signal inputted from a plurality of HART transmitters from first HART data, convert the analog signal to digital data, transmit the first HART data to a second signal processing unit, and transmit second HART data received from the second signal processing unit to at least one of the plurality of HART transmitters; and the second signal processing unit configured to control the first signal processing unit and storing conversion result.

Abstract: The disclosed apparatus may include a memory device that stores firmware intended for a plurality of adaptive equalizer devices that equalize communication signals received via a plurality of communication channels. The disclosed apparatus may also include a controller circuit communicatively coupled to the memory device. The controller circuit may detect a power-on event during which the plurality of adaptive equalizer devices begin to receive electrical power. In response to detecting the power-on event, the controller circuit may initialize the plurality of adaptive equalizer devices by writing at least a portion of the firmware stored in the memory device to each of the plurality of adaptive equalizer devices. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A system comprising a peripheral having a timing mechanism and a node, one of which comprises a real memory space and the other a corresponding virtual memory space, is disclosed. On receiving a timing command in the real memory space, comprising references to an event and time, an entry comprising data relative to the event and time references is created in a monitoring queue of the peripheral. A current point in time is then compared, in the peripheral, to a scheduled point in time linked to an item of data relative to a time reference stored in the monitoring queue. In response, if the current point in time is after the scheduled point in time, an item of data relative to a reference linked to the item of data relative to a time reference stored in the monitoring queue is stored in the real memory space.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A bidirectional communication method between a master terminal and a slave terminal on a single transmission line includes the master terminal transmitting an initial message, a slave number and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits an address of the slave terminal and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits data and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits a master No-acknowledgement signal. And the slave terminal transmits a slave acknowledgement signal.