Abstract: Provided herein are approaches to re-factor, rationalize, and prioritize a service model, and to assess service exposure in the service model. At least one approach provides: determining a granularity of one or more services of the service model; re-factoring and refining a service portfolio and a hierarchy of the service model; adapting a Service Litmus Test (SLT) and service exposure scope to the service model; applying Service Litmus Tests (SLTs) to the service model; and verifying, with each affected stakeholder associated with the service model, that the service model achieves business and technical needs based on the results of the SLTs, which include tests to make exposure decisions, including whether to expose the service or not expose the service, wherein the service represent business capabilities and are placed in the hierarchy of the service model which represents the granularity.

Abstract: A method, system and computer readable medium for presenting unique Serial Attached Small computer system interface (SAS) target devices through a single target device. The method includes embedding a SAS protocol chip within an initiator-connectable device, the SAS protocol chip having storage for at least two SAS addresses and configured to select a single address, loading two or more SAS addresses into the SAS protocol chip, and mapping a respective SAS address to one of the unique target devices. The system includes a SAS protocol chip having storage for at least two SAS addresses and a method for selecting a single SAS address, and a processor unit connected to the SAS protocol chip by an interface bus, the processor configured to load two or more identifier addresses into the SAS protocol chip. The computer readable medium contains instructions that cause a processor to perform the described methods.

Abstract: There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Abstract: An extension point virtualization system uses operating system-provided reparse points to provide minimal extension point registration. Reparse points preserve application isolation while removing the scale problem of writing custom extension point proxies for each extension point. Instead, the system can use a single file system filter that generically handles application virtualization reparse points, and store reparse point data for extension points that need redirection. Many extension points can be handled by redirecting the operating system from a typical location for an application resource to a virtualized safe location for the application resource. Thus, the system simplifies the process of handling new extension points by allowing an application virtualization system to simply register new locations that should be handled with reparse points and to then handle registered locations generically.

Abstract: A method and system defines a mechanism to architect and define extensible methods and processes to build hybrid solutions. Solution templates provide a mechanism to architect and define the software development method in an extensible way and it enables the method architecture to be flexible to assemble method content and process elements only for those solution types that are necessary for a given solution. Solution templates keep the common base method lightweight and reusable and control the proliferation of software development processes necessary to build hybrid solutions by defining the solution templates for each of the solution types as pluggable extensions or add-ons to the base method that can be assembled on demand based on project needs.

Abstract: An arithmetic unit which includes: a data supply section which supplies floating-point type object data to which a sign is to be added and condition data which includes a condition under which the sign is added; a sign data generating section which extracts the condition included in the condition data and generates sign data for adding the sign to the object data on the basis of the extracted condition; and an integer arithmetic operation section which performs an integer arithmetic operation while treating the object data as integer type data so as to add the sign to the object data on the basis of the sign data and the object data.

Abstract: A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. The frames in the controller are tracked by creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. The controller includes, a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame.

Abstract: A hardened DVI transmitter includes a differential driver to convert a ground-up DVI signal into a balanced DVI signal. The balanced DVI signal is transmitted to a DVI compliant cable, through one or more transformers. Transformers effectively remove direct current interference from sources such as lightning. A hardened DVI receiver receives the balanced DVI signal, from the DVI compliant cable, through one or more complimentary transformers. The balanced DVI signal is then converted back to a ground-up DVI signal. By this method, DVI compliant signals may be sent through DVI cables longer than ten meters, and survive interference from lightning.

Abstract: A method is provided for a network-attached storage (NAS) server to directly write data to a disk or block device within a storage subsystem. A NAS server Ethernet interface receives a file, and writes the file data into kernel space as PDU segments. A TCP/IP stack maps the file data in kernel space RAM as sequentially ordered segments. The NAS/CIFS server application sends a call specifying file storage data. A zero-copy DMA application receives the call, maps a file offset to a Logical Block Address (LBA) in the block device, and requests that the block device DMA application transfer the file data. Without rewriting the file data in the system RAM, the block driver DMA application transfers the file data, in units of file system blocks, directly from kernel space RAM to the block device, with each file system block written in a single write operation.

Abstract: There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Abstract: In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed.

Abstract: A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral.

Abstract: A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.

Abstract: Managing a direct memory access (‘DMA’) injection first-in-first-out (‘FIFO’) messaging queue in a parallel computer, including: inserting, by a messaging unit management module, a DMA message descriptor into the injection FIFO messaging queue; determining, by the messaging unit management module, the number of extra slots in an immediate messaging queue required to store DMA message data associated with the DMA message descriptor; and responsive to determining that the number of extra slots in the immediate message queue required to store the DMA message data is greater than one, inserting, by the messaging unit management module, a number of DMA dummy message descriptors into the injection FIFO messaging queue, wherein the number of DMA dummy message descriptors is at least as many as the number of extra slots in the immediate messaging queue that are required to store the DMA message data.

Abstract: The present invention is to provide a connection device capable of increasing data reading and writing speeds, wherein the connection device includes a first connection module connected to a computer, a second connection module connected to at least one regular storage unit, a high-speed storage unit having higher data reading and writing speeds than each regular storage unit, and a control module respectively connected to the connection modules and the high-speed storage unit for identifying product information of each regular storage unit and the high-speed storage unit and generating a forward mapping table for each regular storage unit and a backward mapping table for the high-speed storage unit. Thus, when the computer performs a reading or writing operation on the regular storage unit, the control module can execute the operation through the high-speed storage unit according to the mapping tables, so as to shorten the time required for data processing.

Abstract: A computer implemented method, apparatus, and computer usable program code are provided for changing functionality for an electronic device. A set of signals is received from a set of sensors in the electronic device. Each signal in the set of signals includes a type of sensor from which the signal originated in the set of sensors and information detected by the set of sensors. An action is identified to be issued for the electronic device. The action is identified using the type of sensor and the information. The action is automatically initiated in the electronic device. The automatically initiated action changes the functionality for the electronic device.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

Abstract: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Abstract: Described herein are methods, systems and machine-readable media that facilitate an analysis of the contributing factors of storage system latency. The variation over time of the storage system latency is measured, along with the variation over time of the activity of various processes and/or components, the various processes and/or components being potentially contributing factors to the storage system latency. The latency measurements are correlated with the process and/or component measurements. High correlation, while not providing direct evidence of the causation of latency, is nevertheless used to identify likely factors (i.e., processes, components) contributing to latency. The latency measurements are plotted over time, the plot including supplemental information indicating, at any time instant, likely factors contributing to the storage system latency.

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.