Patents Examined by Brooke Taylor
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Patent number: 8769171Abstract: A device having a plug that is configured to mechanically interface with a receptacle external to the device. The plug also has an electrical interface that electrically interfaces with the receptacle even though the external receptacle has a mechanical and electrical interface shaped to interface with an integrated cable that includes an optical communication mechanism for communicating over most of the length of the integrated cable, and even though the device itself has a full electrical communication channel communicatively coupling a data communication endpoint of the device with the electrical interface of the plug.Type: GrantFiled: April 4, 2008Date of Patent: July 1, 2014Assignee: Finisar CorporationInventors: Lewis B. Aronson, Darin James Douma
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Patent number: 8739111Abstract: The method of the present invention to re-factor, rationalize, and prioritize a service model and to assess service exposure in the service model is illustrated. The service model is reviewed and re-factored and the service portfolio and service hierarchy are refined, exposure decisions are made, and finally the service model and its constituent parts are rationalized based on the re-factoring and exposure decisions. Another technique called Service Litmus Tests (SLTs) is leveraged during service re-factoring and rationalization. SLTs are set of gating criteria to select and filter a set of (candidate) services from the service portfolio for exposure. A Service Exposure Assessment Toolkit (SEAT) is also presented in the present invention. SEAT is a mathematical model to facilitate making exposure decisions for services and prioritizing the services in the service model.Type: GrantFiled: February 2, 2010Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Abdul Allam, Ali P. Arsanjani, Shuvanker Ghosh, Kerrie L. Holley
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Patent number: 8725906Abstract: A Storage Area Network (SAN) system has host computers, front-end SAN controllers (FE_SAN) connected via a bus or network interconnect to back-end SAN controllers (BE_SAN), and physical disk drives connected via network interconnect to the BE_SANs to provide distributed high performance centrally managed storage. Described are hardware and software architectural solutions designed to eliminate I/O traffic bottlenecks, improve scalability, and reduce the overall cost of SAN systems. In an embodiment, the BE_SAN has firmware to recognize when, in order to support a multidisc volume, such as a RAID volume, it is configured to support, it requires access to a physical disk attached to a second BE_SAN; when such a reference is recognized it passes assess commands to the second BE_SAN. Further, the BE_SAN has firmware to make use of the physical disk attached to the second BE_SAN as a hot-spare for RAID operations.Type: GrantFiled: December 31, 2012Date of Patent: May 13, 2014Inventor: Branislav Radovanovic
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Patent number: 8707009Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.Type: GrantFiled: September 26, 2012Date of Patent: April 22, 2014Assignee: Rambus Inc.Inventor: Ian Shaeffer
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Patent number: 8701098Abstract: A method, apparatus and program product are provided for parallelizing analysis and optimization in a compiler. A plurality of basic blocks and a subset of data points of a computer program is prepared for processing by a main thread selected from a plurality of hardware threads. The plurality of prepared basic blocks and subset of data points are placed in a shared data structure by the main thread. A prepared basic block of the plurality of prepared basic blocks and/or a tuple associated with the subset of data points is concurrently retrieved from the shared data structure by a work thread selected from the plurality of hardware threads. A compiler analysis or optimization is performed on the prepared basic block or tuple by the work thread.Type: GrantFiled: April 2, 2009Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Robert R. Roediger, William J. Schmidt
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Patent number: 8688868Abstract: A computer system may comprise a second device operating as a producer that may steer data units to a first device operating as a consumer. A processing core of the first device may wake-up the second device after generating a first data unit. The second device may generate steering values after retrieving a first data unit directly from the cache of the first device. The second device may populate a flow table with a plurality of entries using the steering values. The second device may receive a packet over a network and store the packet directly into the cache of the first device using a first steering value. The second device may direct an interrupt signal to the processing core of the first device using a second steering value.Type: GrantFiled: September 2, 2011Date of Patent: April 1, 2014Assignee: Intel CorporationInventors: Anil Vasudevan, Partha Sarangam, Ram Huggahalli, Sujoy Sen
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Patent number: 8661422Abstract: Methods, apparatus and computer software product for local memory compaction are provided. In an exemplary embodiment, a processor in connection with a memory compaction module identifies inefficiencies in array references contained within in received source code, allocates a local array and maps the data from the inefficient array reference to the local array in a manner which improves the memory size requirements for storing and accessing the data. In another embodiment, a computer software product implementing a local memory compaction module is provided. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to improve the efficiency of data storage in array references. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.Type: GrantFiled: February 4, 2009Date of Patent: February 25, 2014Assignee: Reservoir Labs, Inc.Inventors: Richard A. Lethin, Allen K. Leung, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
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Patent number: 8650336Abstract: The direct memory access device and method of the present invention uses an event calendar, an expired event queue of a fixed size, a calendar scanner, and an event mover. The event calendar stores an event in a linked list. The expired event queue stores an event that has already expired from the event calendar. The calendar scanner automatically scans the event calendar without management by a central processing unit (CPU). The event mover moves an event from the event calendar to the expired event queue without management by the CPU. The method provides for storing the event in the linked list, automatically scanning the event calendar without management by the CPU, moving the event from the event calendar to an expired event queue of a fixed size without management by the CPU, and storing the event that has already expired from the event calendar.Type: GrantFiled: October 27, 2006Date of Patent: February 11, 2014Assignee: Alcatel LucentInventors: Roger Maitland, Hal Ireland, Eric Combes, Kevin Smith
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Patent number: 8615741Abstract: An apparatus, system, and method are disclosed for improved tracking of software item defects. The approach involves maintaining defect attributes for a particular software bug. Certain attributes are user-defined while others are derived. Attributes may be, for example, questions, requests for action, requests for approval, or others. The primary attributes and derived attributes for the bug are associated with users that are associated with the software bug, and a determination is made as to whether or not action is required by the individual users for the software bug using the attributes. If action is required, the user is alerted that action is required for the software bug. The actions and/or bugs may be presented to the user using an inbox format. The inbox may sort actions based on priority, what type of attribute is relevant to the user, or using other categorizations.Type: GrantFiled: December 24, 2009Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventor: Thomas R. Hudson
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Patent number: 8612930Abstract: Methods and apparatus for dynamic class reloading and versioning that allow developers to change and recompile classes and to have running programs adopt the new versions of the classes dynamically, without redeploying the application. A dynamic class reloading component detects if the environment supports dynamic class redefinition and uses it if supported but does not require it. As the component loads a managed class, it modifies the bytecode of the class and generates additional classes and interfaces to support type-safe class versioning. Unique names are generated for successive versions of a managed class. A separate interface may be generated for each distinct method name and signature implemented on managed classes. Each generated class may implement all the generated interfaces that correspond to its methods. The same class loader that would load each managed class without the component loads the component-generated classes and interfaces.Type: GrantFiled: January 30, 2009Date of Patent: December 17, 2013Assignee: Oracle America, Inc.Inventors: Timothy J. Quinn, John R. Rose
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Patent number: 8612654Abstract: A method of determining configuration parameters of a mobile network topology for testing and monitoring purposes at an interface (Iub) located between a first node and a second node of the mobile network where between the first and the second node there exist several channels includes finding the channel having signaling information, analyzing signaling information to determine the configuration parameters, updating the configuration parameters dynamically, and performing a monitoring activity or test scenario based on the configuration parameters.Type: GrantFiled: January 12, 2012Date of Patent: December 17, 2013Assignee: Tektronix, Inc.Inventor: Max Schreiber
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Patent number: 8612644Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.Type: GrantFiled: May 31, 2011Date of Patent: December 17, 2013Assignee: Hitachi, Ltd.Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
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Patent number: 8572588Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.Type: GrantFiled: March 31, 2009Date of Patent: October 29, 2013Assignee: Nvidia CorporationInventors: Vinod Grover, Bastiaan Joannes Matheus Aarts, Michael Murphy
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Patent number: 8560745Abstract: A storage device includes a data storage section, a first control section, a communication section, a second control section and a wireless transmission/reception section. The data storage section stores data. The first control section controls reading and writing the data from and into the data storage section. The communication section transmits and receives the data through a transmission line to and from a host device. The second control section transmits and receives the data to and from the first control section and the communication section. The wireless transmission/reception section is connected to the first and second control sections, is directed toward a predetermined direction, and wirelessly transmits and receives data to and from another storage device provided in the predetermined direction.Type: GrantFiled: March 3, 2009Date of Patent: October 15, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Shinobu Ozeki, Masaru Kijima, Junji Okada
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Patent number: 8527671Abstract: Disclosed herein is a method of accessing a slave device from a circuit including a central processing unit, a data transfer engine, and an interface to the slave device. In one embodiment, the method includes: executing code on the central processing unit to set up the data transfer engine to access the slave device; and based on the set-up, operating the data transfer engine to supply a read request word to a transmit buffer of the interface for transmission to the slave device, and, after return of a corresponding response word to a first-in-first-out receive buffer of the interface, to disable the first-in-first-out receive buffer from receiving any further data such that the last word therein is assured to be the response word. The method further includes using an underflow mechanism of the first-in-first-out receive buffer to determine the last word therein and hence determine the response word.Type: GrantFiled: December 21, 2009Date of Patent: September 3, 2013Assignee: Icera Inc.Inventor: Andrew Glyn Bond
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Patent number: 8479181Abstract: Techniques for performing capacity planning for applications running on a computational infrastructure are provided. The techniques include instrumenting an application under development to receive one or more performance metrics under a physical deployment plan, receiving the one or more performance metrics from the computational infrastructure hosting one or more applications that are currently running, using a predictive inference engine to determine how the application under development can be deployed, and using the determination to perform capacity planning for the applications on the computational infrastructure.Type: GrantFiled: February 1, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Henrique Andrade, Bugra Gedik, Andrew L. Frenkiel, Rohit M. Kandekar, Joel L. Wolf, Kun-Lung Wu
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Patent number: 8473921Abstract: Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.Type: GrantFiled: December 23, 2009Date of Patent: June 25, 2013Assignee: Microsoft CorporationInventors: Martin Taillefer, Ali-Reza Adl-Tabatabai, Gad Sheaffer, Peter Lachner, Richard Wurdack, Darek Mihocka, Jan Gray
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Patent number: 8473644Abstract: Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g.Type: GrantFiled: March 4, 2009Date of Patent: June 25, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sanjay Deshpande, Jaideep Dastidar
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Patent number: 8463959Abstract: A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.Type: GrantFiled: January 24, 2011Date of Patent: June 11, 2013Assignee: Mosaid Technologies IncorporatedInventor: Byoung Jin Choi
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Patent number: 8464231Abstract: A method and apparatus access a production among first and second groups of productions. The productions form rules for constructing hierarchical data of a structured electronic document. The first group is associated with a first group of events, each production being defined for an event type and contextual information including a name associated with an element in the hierarchical data. The second group is associated with a second group of events distinct from the first group of events, the events of the second group describing the hierarchical data of the structured electronic document. The device determines whether an event is of the first group including determining whether the event in question is defined by a name associated with an element in addition to an event type, and predicts a production from the second group that is associated with the event is determined to be of the first group.Type: GrantFiled: February 11, 2009Date of Patent: June 11, 2013Assignee: Canon Kabushiki KaishaInventor: Romain Bellessort