Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract: A device, which has not obtained a resource, can securely obtain a required resource without degradation in response to resource obtainment, and obtains the resource which is exclusively controlled between the device and another device. The device includes: a status detector which detects a status of the other device; a resource obtainer which includes flag information and obtains the resource based on the flag information, the flag information indicating whether the obtainment of the resource is permitted or prohibited; and a determiner which switches the flag information to indicate whether the obtainment is permitted or prohibited, based on the status of the other device detected by the status detector. The resource obtainer is prohibited from obtaining the resource when the flag information indicates that the obtainment is prohibited.

Abstract: A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.

Abstract: A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories.

Abstract: To schedule workloads of requesters of a shared storage resource, a scheduler specifies relative fairness for the requesters of the shared storage resource. In response to the workloads of the requesters, the scheduler modifies performance of the scheduler to deviate from the specified relative fairness to improve input/output (I/O) efficiency in processing the workloads at the shared storage resource.

Abstract: An accelerated access apparatus and reading and writing methods thereof are described. A processing unit is used to determine whether the continuation state of a plurality of first address parameters of first request signals. Each first request signal has a first address length. When the first address parameters are continuous thereamong, the processing unit converts one of the second request signals into a second reading command which has a second reading address and a second reading address length. The second reading address length is greater than one of the first address lengths. The processing unit executes the second reading command to read data content to be stored in a buffer unit based on the second reading address and the second reading address length for responding to the second request signals.

Abstract: An apparatus and method implemented in hardware and embedded software that improves performance, scalability, reliability, and affordability of Storage Area Network (SAN) systems or subsystems. The apparatus contains host computers (application servers, file servers, computer cluster systems, or desktop workstations), SAN controllers connected via a bus or network interconnect, disk drive enclosures with controllers connected via network interconnect, and physical drive pool or cluster of other data storage devices that share I/O traffic, providing distributed high performance centrally managed storage solution. This approach eliminates I/O bottlenecks and improves scalability and performance over the existing SAN architectures.

Abstract: Some of the embodiments of the present disclosure provide a method comprising coupling a first device to a client device, the first device having a virtual storage drive, the virtual storage drive storing a device driver; installing the device driver in the client device; and subsequent to installation of the device driver in the client device, installing a filter driver in the client device, the filter driver configured to prevent the client device from detecting the virtual storage drive of the first device whenever the first device is subsequently re-coupled to the client device. Other embodiments are also described and claimed.

Abstract: Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode.

Abstract: A non-volatile memory device having a USB connector with a USB controller, and a wireless antenna with a wireless controller. The USB controller and the wireless controller are both operatively connected to the non-volatile memory. When the non-volatile memory device is operatively connected to a host using the USB connector, the USB controller has priority over the wireless controller for read from, and write to, functions with the non-volatile memory. A corresponding method is also disclosed.

Abstract: The correspondence of the respective ports and the respective microprocessors is dynamically changed based on the load of the respective microprocessors. When an open port MP including a plurality of ports connected to a host computer receives an I/O request from the host computer via a port, it specifies an MPPK to become the transfer destination of the I/O request, and transfers the I/O request to the specified MPPK. Each MP belonging to the MPPK that received the I/O request selects either an exclusive mode where a single MP exclusively performs the processing of the I/O request, or a share mode where two or more MPs share the processing of the I/O request. Each MP selects the exclusive mode or the share mode corresponding to when load information concerning the ports shows a low load or high load condition, respectively, and executes the I/O processing accordingly.

Abstract: A method and device of enabling interoperation between different devices over a network are provided. A test code corresponding to a service to be performed using device information received from a service providing device in a network is generated, the test code is transmitted to the service providing device, a result of the test code execution is received from the service providing device, and interoperability with the service providing device is determined with respect to the service by using the result of the execution of the test code. An environment suitable for interoperation with the service providing device is established when interoperation with the service providing device is possible.

Abstract: A system and method is disclosed in which a switch is located between the I/O hubs of the computer system. The I/O hubs are coupled to I/O devices of the computer system. The I/O hubs are also coupled to one or more processors via direct point-to-point communication links. The I/O hub provides a connection point between various I/O devices and processors. The switch includes a set of internal communications pathways that can be set according to the communication status of links between the processors and I/O hubs of the system. When the communication links of the system are operational, the switch allocates all of I/O hub transmission bandwidth to I/O devices. When the communication links are determined to be not operational, the switch allocates some of I/O hub transmission bandwidth to establish a communication link between the I/O hubs of the computer system, while the remaining I/O hub transmission bandwidth is allocated to I/O devices.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A data communication apparatus 1 has a processing section (CPU) 10 that executes at least a part of communication processing of a communication controller 2 and that executes processing other than the communication processing, wherein The data communication apparatus 1 has an interrupt request blocking section 20 that blocks, during execution of a processing relevant to information exchange concerning a communication condition for the communication controller 2 to carry out a communication processing, an interrupt request to the processing section 10 with priority over the processing relevant to information exchange. With this arrangement, even when additional operation is carried out to execute an interrupt processing during execution of a processing concerning a communication condition such as a modulation system of a modem and a communication speed, the processing can be executed securely and a stable connection of a communication line can be maintained.

Abstract: In PCI-Express and alike communications systems, number of lanes used per channel or port can vary as a result of negotiated lane aggregation during network bring-up. Disclosed are systems and methods for efficiently realigning packet data and stripping out control bytes in a by-eight port configuration as the packet data ingresses from the physical layer (PL), past the data link layer (DL) and into the transaction layer (TL). It is shown that data routing can be reduced to just two, mux-selectable permutations based on whether the STP (start of packet) character arrives in an even numbered double-word side (DW0) or an odd-numbered double-word side (DW1) of a physical layer register.

Abstract: A storage and a controller each include an assignment number-managing unit for managing the number of command-processing resources assigned corresponding to a command-sending/receiving pair in combination of an external device and a logical device receiving a data input/output-requiring command; and an assignment-controlling unit for assigning the data input/output-requiring command to the command-processing resource corresponding to the command-sending/receiving pair, the number of the command-processing resources being equal to or lower than the number to be assigned that is managed by the assignment number-managing unit.

Abstract: The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network, the storage cluster including at least a first target device and a second target device. The method includes receiving an input/output (I/O) at the first target device from the initiator via the network. The I/O includes a data request. The method further includes transmitting a SCSI I/O referral list to the initiator when data included in the data request is not stored on the first target device, but is stored on the second target device. The referral list includes first and second port identifiers for identifying first and second ports of the second target device respectively. The first and second ports of the target device are identified as access ports for accessing the data requested in the data request.

Abstract: Methods and systems are disclosed for detecting DisplayPort (DP) source device connection to sink devices. When the DP link is active, no measurements are made to determine source device connections. When a DP link is not active, a signal line for the auxiliary channel for a DP connection is measured to determine if a source device is connected. More particularly, the auxiliary channel is a differential auxiliary channel, and the positive signal line is measured to make the determination of whether a source device is connected. Still further, an indication is made that a source device is connected if the positive signal line is at a low level, and an indication is made that a source device is not connected if the positive signal line is at a high level.