Abstract: An apparatus for operating an external manual battery charger having a first AC power input and a DC charging output. The apparatus includes an AC controller configured to adjust at least one power parameter supplied to the AC power input of the external manual battery charger. The power parameter(s) may be any one or more of AC current, AC voltage and AC power. The apparatus further includes a feedback converter configured to monitor at least one charging parameter and to control the AC controller to adjust the one or more power parameters in accordance with the monitored charging parameter or parameters.

Abstract: The invention relates to a device for the charge equalization of an energy accumulator arrangement, and to a method for the charge equalization of accumulator modules of an energy accumulator arrangement.

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A power system adapted for supplying power in a high temperature environment is disclosed. The power system includes a rechargeable energy storage that is operable in a temperature range of between about seventy degrees Celsius and about two hundred and fifty degrees Celsius coupled to a circuit for at least one of supplying power from the energy storage and charging the energy storage; wherein the energy storage is configured to store between about one one hundredth (0.01) of a joule and about one hundred megajoules of energy, and to provide peak power of between about one one hundredth (0.01) of a watt and about one hundred megawatts, for at least two charge-discharge cycles. Methods of use and fabrication are provided. Embodiments of additional features of the power supply are included.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.

Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.

Abstract: A pattern inspection apparatus according to an embodiment includes an image capture and an output part. The image capture captures an image of a second pattern of an inspection target object obtained by enlarging the inspection target object having a first pattern. The output part outputs position information of the first or second pattern corresponding to divergent portions between a reference data generated from design data of the first pattern and a captured data generated by the image capture, other than prediction positions of first defects occurring when the inspection target object is enlarged.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

Abstract: A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.

Abstract: A computer program product for performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

Abstract: A graph is constructed, having a plurality of nodes representing a plurality of logical operations and a plurality of edges connecting those of the plurality of nodes which do not conflict. A weight, including a width difference between end nodes of each of the edges, is assigned to each edge. Weighted cliques are enumerated, each including at least two of the nodes. Each of the weighted cliques is replaced with a single one of the logical operations and a multiplexer, to obtain a plurality of multiplexer-operation groups, such that each logical operation in one of the multiplexer-operation groups can be shared within a same clock cycle of a digital electronic integrated circuit.