Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes reducing the set of candidate interconnects for layer promotion based on resource availability. A method of managing includes identifying a set of candidate interconnects for the layer promotion, scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank, and assessing routing demand and resource availability based on promoting the set of candidate interconnects. The method also includes managing the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects.

Abstract: A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.

Abstract: A battery module includes a plurality of battery units, each of which supplies electrical power to a load through a respective linear regulator. In a method for managing supply of electrical power by the battery module, a number of battery units that supply electrical power to the load is controlled according to magnitude of a current required by the load, so as to reduce power loss in the linear regulators.

Abstract: A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance.

Abstract: A method for monitoring and optimizing operation of a terminal, including: generating an output voltage equal to a first DC value; connecting a vehicle, the output voltage switching to a second value; authorizing charging of the vehicle by modulating the output voltage between two values, with a maximum authorized charge current being set; checking an ability of the vehicle to be recharged by monitoring a value of the output voltage; supplying an output voltage modulated between a third voltage value and a negative value; initializing a first timer; reading a diagnosis time between initialization and the switching of the voltage from the second to the third value; comparing the time with standard values to determine a type of charger; taking characteristics of the charger into account to optimize energy management.

Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.

Abstract: A wind load resistant, tracking photovoltaic solar array system may include a pivot support; at least one solar cell coupled to the pivot support; and a pivot arm coupled to the solar cell for providing transverse movement of the solar cell relative to a longitudinal axis of the pivot support. A transverse drive motor may be coupled to the pivot arm for rotating the pivot arm in response to control signals. A tube for housing the solar cell, pivot arm, and the transverse drive motor may also be included. A support structure may be coupled to the tube and for mounting the tube against another structure, such as a building rooftop. A longitudinal axis drive motor may be coupled to the tube and the support structure. The longitudinal axis drive motor may rotate the tube around a geometrical longitudinal axis of the tube in response to control signals.

Abstract: Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.

Abstract: Systems and methods for enhancing performance of programs implemented on an integrated circuit (IC) are provided. A forward-flow selector may determine a common branch for adding a data set to and removing a data set from. By selecting a common branch for adding and removing a data set, there will be a pipeline stage for data flowing into the branch. Accordingly, the embodiments described herein enhance throughput by increasing the number of datasets that may enter a branched pipeline without stalling.

Abstract: A battery charger (1000) non-concurrently performing a first operation to charge a main battery (MBA) and a sub-battery (SBA) by using an external power supply (AC), and a second operation to charge the sub-battery by using the main battery, including: a power supply circuit (1); a transformer (3); a secondary-side circuit (4) rectifying a voltage induced in a winding (302) and supplying the voltage to the main battery in a first time period for the first operation, and converting a DC voltage from the main battery into an AC voltage and supplying the AC voltage to the winding in a second time period for the second operation; a conduction angle adjustment circuit (7); and a control circuit (10), the secondary-side circuit being a full-bridge circuit including parallel-connected arms each including parallel-connected bodies connected in series, the parallel-connected bodies each including a switching unit and a rectifying unit connected in parallel.

Abstract: A method of generating a pixel array layout for an image sensor (wherein the image sensor includes a plurality of unit pixels, and each of the plurality of unit pixels includes a plurality of transistors) includes forming each unit pixel to include a shallow trench isolation (STI). The STI is between a deep trench isolation (DTI) area and one of a p-well region and source and drain regions of each transistor. The p-well region is below a gate of each of the transistors, and the DTI area is filled with at least two materials.

Abstract: Disclosure is related to a reconfigurable sorter and a method of sorting using the sorter. The reconfigurable sorting method is adapted to the sorter essentially consisting of multiple serially-connected comparison units. The each comparison unit includes two registers. The sorter is particularly a reconfigurable device according to the number of sorted numerals. According to the exemplary embodiment, an input mode is initiated firstly. Initial values are set to the registers. The numerals are sequentially inputted to the registers. At the input mode, the values in the registers may be shifted if necessary and mutually compared in every comparison unit. The values in the registers of every comparison unit may be swapped based on the comparison. At output mode, the numerals are outputted sequentially. The values in the registers are shifted and swapped until all numerals are completely outputted. The output appears the sorted numerals with low timing latency.

Abstract: Modifying a circuit includes: obtaining timing information of the circuit, wherein the timing information includes timing information pertaining to a critical path of the circuit; determining a scope associated with the critical path, the scope including a subset of the circuit; and performing a fix based at least in part on physical information associated with the circuit to improve timing of the scope.

Abstract: A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target regions to a frequency profile of layout patterns in the reference baseline; and based on the comparison, utilizing the processor to identify candidate layout patterns from the set of target regions for further analysis.

Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract: A method and a system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.

Abstract: Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design. A connectivity graph is generated based on the target layout in which lines of the backbone features are represented as nodes on the connectivity graph. The nodes are connected based on spacer patterning process limitations and the connections are assigned to sets. A backbone mask layout is then generated based on one of the sets of nodes.