Patents Examined by C. Everhart
  • Patent number: 7084028
    Abstract: A semiconductor device comprises a semiconductor substrate having a cavity region inside; a first insulation film formed on the inner wall of the cavity region; a first electrode formed on the inner wall of the first insulation film in the cavity region, and having a hollow cavity inside; a semiconductor region overlying the cavity region and including first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type which are adjacent to each other, said semiconductor region having a bottom surface on which the first electrode is formed via the first insulation film; a second insulation film covering the top surface of the semiconductor region; and a second electrode formed on the semiconductor region via the second insulation film and electrically insulated from the semiconductor region and the first electrode.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: August 1, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Patent number: 7026257
    Abstract: A method is used for forming a low relative permittivity dielectric film by a vacuum ultraviolet CVD. The film is a silicon organic film (e.g., SiOCH, SiC, SiCH, and SiOF films) that has a controlled relative permittivity and is formed at temperatures below 350° C. The method can control the content of carbon in the film to achieve a desired relative permittivity. A desired relative permittivity can be achieved by: {circle around (1)} controlling the type and flow rate of added gas (O2, N2O) that contains oxygen atoms; {circle around (2)} controlling the flow rate of TEOS; {circle around (3)} controlling the intensity of light emitted from the excimer lamp; {circle around (4)} elevating the temperatures of the synthetic quartz window and the gas flowing in the vacuum chamber, and controlling the distance between the synthetic quartz window and the wafer; and {circle around (5)} controlling the temperature of the wafer.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 11, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kiyohiko Toshikawa, Yoshikazu Motoyama, Yousuke Motokawa, Yusuke Yagi, Junichi Miyano, Tetsurou Yokoyama, Yutaka Ichiki
  • Patent number: 6887772
    Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: May 3, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dae Woo Lee, Tae Moon Roh, Yil Suk Yang, Il Yong Park, Byoung Gon Yu, Jong Dae Kim
  • Patent number: 6787381
    Abstract: A semiconductor laser capable of emitting a plurality of laser light having different oscillation wavelengths which is formed with dielectric films having little fluctuation in reflectance at ends of a plurality of active layers and a method of production of the same, said semiconductor laser having a plurality of active layers having different compositions on a substrate and emitting in parallel a plurality of laser light having different oscillation wavelengths, wherein a front dielectric film having a predetermined thickness by which a reflectance with respect to light of a predetermined wavelength of an arithmetical mean of oscillation wavelengths becomes the extremal value is formed on an end of the laser emission side, while rear dielectric films having higher reflectances compared with the front dielectric film and having predetermined thicknesses by which reflectances with respect to light having a predetermined wavelength become the extremal values are formed on the end of the rear side, and a method
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: September 7, 2004
    Assignee: Sony Corporation
    Inventor: Kazuhiko Nemoto
  • Patent number: 6475874
    Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: November 5, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qi Xiang, Paul R. Besser, Matthew S. Buynoski, John C. Foster, Paul L. King, Eric N. Paton
  • Patent number: 6376271
    Abstract: A dry film resist is used to form an interlayer insulating film in a process for fabricating a liquid crystal display device of the POP structure. The dry film resist is formed by applying a photosensitive resin on a base film to a uniform thickness, and a protective film layer is formed on a surface of the photosensitive resin film thus formed. From the dry film resist guided to the vicinity of a glass substrate, the protective film is removed immediately before transfer. Then, the photosensitive resin is heated and pressed against the foregoing glass substrate by a transfer roller, whereby the interlayer insulating film is formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 23, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Sawayama, Kazuhiko Tsuda, Shigeaki Mizushima
  • Patent number: 6320269
    Abstract: A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: November 20, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Sen-Fu Chen, Kuei-Jen Chang
  • Patent number: 6281585
    Abstract: A high speed interconnect structure and methods for making the structure are provided. The interconnect structure includes a first metallization layer having a plurality of metallization lines and a conductive via metallization layer defined over the first metallization layer. The conductive via metallization layer is configured to define self-aligned conductive vias. A non-conformal oxide layer is defined over the first metallization layer and the conductive via metallization layer such that air gaps are positioned between the plurality of metallization lines. A cap oxide layer is then defined over the non-conformal oxide. In this example, a CMP operation can be performed to expose the top surfaces of the conductive vias before a next metallization layer is defined. It should be noted that air gaps are defined without the problems associated with conductive via misalignment.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 28, 2001
    Assignee: Philips Electronics North America Corporation
    Inventor: Subhas Bothra
  • Patent number: 6180520
    Abstract: The present invention relates to an interconnect structure wherein the upper surface of the first interconnect level is a tungsten layer, portions of the first interconnect level are insulated from one another by an insulator of the SOG type, portions of a second interconnect level are connected to portions of the first interconnect level by conductive pads formed in openings of an insulating layer, at least the lower part of which is of the SOG type, the walls and the bottom of the openings are covered with a thin titanium layer, and the openings are filled with a conductive material selected in the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: January 30, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Michel Marty, G{acute over (e)}rard Passemard, Graeme Wyborn
  • Patent number: 6133635
    Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: October 17, 2000
    Assignee: Philips Electronics North America Corp.
    Inventors: Subhas Bothra, Jacob Haskell
  • Patent number: 6121140
    Abstract: A method of producing a thick metal film on a substrate surface with a substantially smooth surface morphology and low resistivity. A substrate is exposed to a plasma. A first thin metal film is deposited on the substrate by chemical vapor deposition. The substrate with the film deposited thereon is exposed to a plasma, and a second thin metal film is deposited on top of the first film. The substrate may undergo subsequent cycles of plasma exposure and film deposition until a desired film thickness is obtained. The resulting film has a smooth surface morphology and low resistivity.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: September 19, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Chantal Arena, Ronald T. Bertram, Emmanuel Guidotti, Joseph T. Hillman
  • Patent number: 6118175
    Abstract: A flexible shelf (12) and a method for coupling a semiconductor chip (33) to a leadframe (23) using the flexible shelf (12). The flexible shelf (12) has a mounting portion (16), a flexible portion (17), and a leadframe support portion (18). The flexible shelf (12) is used in a wire bonding support assembly (10) to provide support for the leadframe (23) during wire bonding. The flexible portion (17) of the flexible shelf (12) flexes to increase thermal conductivity between a heater block (29) and the leadframe (23) during wire bonding.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: September 12, 2000
    Assignee: Motorola, Inc.
    Inventors: Harold G. Anderson, Albert John Laninga, Rodney D. Purcell, Gilbert J. Archibeque, Jr., Stefan M. Dykert
  • Patent number: 6054381
    Abstract: The present invention is a semiconductor device having a plurality of wiring on a semiconductor substrate. It is provided with a first insulating film which covers the surface of all the aforesaid wiring, and a second insulating film containing air gaps which is formed between such of the aforesaid wiring as is mutually adjacent.The method of manufacturing the semiconductor device to which the present invention pertains comprises a process whereby the first insulating film is formed in such a manner as to cover the surface of the plurality of wiring formed on the semiconductor substrate, and a process whereby the second insulating film containing air gaps is formed between such of the wiring on the aforesaid substrate as is mutually adjacent. Here, the first insulating film is formed by means of the plasma CVD or spin coating methods, the second by means of the plasma CVD, spin coating, bias CVD, sputtering or similar methods.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: April 25, 2000
    Assignee: NEC Corporation
    Inventor: Norio Okada
  • Patent number: 5877031
    Abstract: The present invention relates to a method for forming a TiNO metallic barrier layer acting as a diffusion barrier to intercept the diffusing of the Si atoms between metal layers, the method comprising the steps of: forming a TiN film through a sputtering equipment using Ar and N.sub.2 gas; implanting N.sub.2 O gas on the upper part of the TiN film; and annealing the resulting structure at N.sub.2 atmosphere for diffusing oxygen ions, thereby forming said resulting structure into uniform TiNO film.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: March 2, 1999
    Assignee: Hyundai Electronics Industries Co, Ltd
    Inventors: Hyun Jin Jang, Woo Bong Lee, Young Hwa Mun, Young Ho Jeon, Jae Wan Koh, Young Mo Koo, Se Jeong Kim
  • Patent number: 5828131
    Abstract: Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than C., and more preferably between about C.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Lawrence Alfred Clevenger, Francois Max d'Heurle, James McKell Edwin Harper, Randy William Mann, Glen Lester Miles, James Spiros Nakos, Ronnen Andrew Roy, Katherine L. Saenger
  • Patent number: 5804506
    Abstract: A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: September 8, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, Randhir P. S. Thakur, Kirk Prall
  • Patent number: 5786267
    Abstract: Disclosed is an alignment mark for the X directional alignment of a chip area on a semiconductor wafer, for example. The alignment mark comprises recesses and projections formed on a semiconductor substrate. The recesses or projections are repeatedly arranged in the X direction. The X directional width of the recesses or projections is set smaller than the X directional width of a grain on a metal film formed on the recesses and projections or the average particle size, as viewed from above the semiconductor substrate. The projections may be formed by an insulating layer formed on the semiconductor substrate.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: July 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Haraguchi, Masahiro Abe, Wataru Nomura
  • Patent number: 5783459
    Abstract: A metal wiring is fabricated for a semiconductor device by fabricating an metal layer made of, a aluminum alloy on a semiconductor substrate through an insulation layer and an undercoating layer for the metal layer, optically patterning a resist layer for producing a resist pattern, radiating ultraviolet rays onto the resist pattern for curing the resist pattern so that the resist pattern becomes a cured resist pattern, etching the metal layer with reactive gas including chlorine by using the cured resist pattern as a mask so as to produce a metal wiring under the cured resist pattern and ashing the cured resist pattern by down flow ashing of oxygen gas including hydrogen and/or hydrogen monoxide, producing the metal wiring to the semiconductor device, wherein the curing by radiation with ultraviolet rays reduces the amount of decomposed polymer on the pattern resist, and therefore on the metal wiring, which would otherwise have formed as a result of this down flow ashing with oxygen.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: July 21, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Tamotsu Suzuki, Kouichi Kawahara
  • Patent number: 5776834
    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 7, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Avanzino, Darrell M. Erb, Robin Cheung, Rich Klein, Pervaiz Sultan
  • Patent number: 5773359
    Abstract: An interconnect system (31) includes an interconnect bump (29) over an under bump metallurgy (25). The under bump metallurgy (25) includes a barrier layer (26) having a barrier material such as titanium, an adhesion layer (28) having an adhesion material such as copper, and a mixture layer (27) having both the barrier material and the adhesion material. The mixture layer (27) is located between the barrier layer (26) and the adhesion layer (28), and the adhesion layer (28) is located between the mixture layer (27) and the interconnect bump (29). The interconnect bump (29) contains solder and is used as an etch mask when patterning the under bump metallurgy (25).
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: June 30, 1998
    Assignee: Motorola, Inc.
    Inventors: Douglas G. Mitchell, Francis J. Carney, Eric J. Woolsey