Abstract: Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal interconnect stacks. The steps of the method comprise first providing a silicon substrate, which typically comprises an in-process integrated circuit wafer. Next, an insulating passivation layer is provided on the silicon substrate. The next step is the sputtering of a titanium layer of a given thickness over the passivation. Subsequently, an aluminum film of three times the thickness of the titanium layer is sputtered over the titanium layer. The next step comprises annealing the titanium layer and the aluminum film in situ in a metal anneal chamber to form titanium aluminide. Following the in situ anneal, the remainder of the needed aluminum is sputtered over the titanium aluminide and a further passivation layer of titanium nitride is then sputtered over the aluminum.

Abstract: According to the method of manufacturing a semiconductor device having a multilayer interconnection structure, lower wires are formed on a semiconductor substrate. Then, a first reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. After the first reflow SiO.sub.2 film is formed, heat treatment is performed at a predetermined high temperature on the semiconductor substrate on which the first reflow SiO.sub.2 film, and a second reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. The heat treatment step performed after the first reflow SiO.sub.2 film forming step and the second reflow SiO.sub.2 film forming step subsequent thereto are respectively performed at least once.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: An SiOF layer is formed by using as raw material an organic Si compound having Si-F bonds. Since an organic Si compound is used as raw material, an intermediate product being formed during the formation of an SiOF layer is liable to polymerize and has fluidity. Moreover, since the organic Si compound has Si-F bonds, low in bond energy, and is thus capable of easily getting only Si-F bonds separated, the SiOF layer is prevented from getting contaminated by reaction by-products and fluorine can be introduced into the SiOF layer in stable fashion. Therefore, an insulator layer, low in dielectric constant, low in hygroscopicity and excellent in step coverage, can be formed by using a low powered apparatus.

Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least he layers of mutually different conductive types, comprises a first portion principally composed of a component same as the principal component of the semiconductor layers, and a second portion consisting of a metal.

Abstract: This invention provides a method for forming dense electrode patterns having a high aspect ratio in a conductor metal layer. The method uses silicon nitride deposited using plasma enhanced chemical vapor deposition, PECVD, as an etch stop mask to protect the conductor metal and anti reflection coating when etching the electrode patterns. The PECVD silicon nitride is also used a mask to eliminate pattern dependence when forming inter-metal dielectric layers. The PECVD silicon nitride is also used as an etch stop mask when forming vias in the inter-metal dielectric for electrical conduction between electrode pattern layers.

Abstract: A layered dielectric structure is provided, which separates a first layer of metal interconnects from each other in semiconductor devices and also separates the first layer from a second, overlying layer of metal interconnects for making electrical contact to the first layer of metal interconnects. The layered dielectric structure comprises: (a) a layer of an organic spin-on-glass material filling gaps between metal interconnects in the first layer of metal interconnects; (b) a layer of an inorganic spin-on-glass material to provide planarization to support the second layer of metal interconnects; and (c) a layer of a chemically vapor deposited oxide separating the organic spin-on-glass layer and the inorganic spin-on-glass layer. The layered dielectric structure provides capacitances on the order of 3.36 to 3.46 in the vertical direction and is about 3.2 in the horizontal direction. This is a reduction of 10 to 15% over the prior art single dielectric layer, using existing commercially available materials.

Abstract: A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer.

Abstract: An apparatus and method for performing a chemical vapor deposition (CVD) procedure to deposit an insulating layer when fabricating semiconductor integrated circuit devices over a silicon wafer. The CVD apparatus includes a buffer chamber for temporarily holding the wafer, and a chemical vapor deposition reaction chamber arranged at the periphery of the buffer chamber and communicating with the buffer chamber via a first access door. The CVD apparatus additionally includes a heating chamber, also arranged at the periphery of the buffer chamber, and communicating with the buffer chamber via a second access door, for performing a heating treatment of the wafer before the insulating layer is deposited on the wafer in the CVD reaction chamber. A transport arm is provided for transporting the wafer into and out of the heating chamber and the chemical vapor deposition reaction chamber.

Abstract: A transfer metal configuration and fabrication process possessing increased probability of intersecting a transverse metallization level are presented, without employing an increase in actual metal thickness. The transfer metal is configured with a non-rectangular transverse cross-section such that the thickness of the electrical connect remains the same, but the transverse contact area of the exposed metal is increased. The entire transfer metal may have the same transverse cross-sectional configuration or have portions with different transverse configurations. If different configurations are employed, each portion of the transfer metal to be transversely intersected has the enhanced cross-sectional configuration. A tiered transverse configuration is presented which facilitates electrical connection of the transfer metal to a metal level on a face of a semiconductor cube structure.

Abstract: A method for plasma hardening a patterned photoresist layer. There is first provided a semiconductor substrate which has formed upon its surface a patterned photoresist layer. The patterned photoresist layer is then exposed to a hydrogen containing plasma for a time sufficient to harden the patterned photoresist layer against a Reactive Ion Etch (RIE) etch plasma to which the patterned photoresist layer is later exposed. A blanket layer residing beneath the plasma hardened photoresist layer may then be patterned through the Reactive Ion Etch (RIE) etch plasma without softening, erosion and/or consumption of the plasma hardened patterned photoresist layer.

Abstract: A method for forming a semiconductor device comprises the steps of forming first and second conductive lines having a space therebetween over a substrate, said first and second conductive lines each having a sidewall. A conductive spacer is formed over each sidewall, and an insulation layer is formed over the conductive spacers. First and second portions of the insulation is removed to form first and second openings therein, thereby exposing the spacers. The exposed portions of the spacers are removed. The conductive spacers form a conductive path between the first and second openings which would short any conductor formed in the first and second openings. To prevent shorting, a second protective layer is formed within the first and second openings which covers a portion of the spacers to remove the conductive path.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: A method for forming a plug in a semiconductor device comprising the steps of: providing openings which expose an underlying layer through an insulating layer; filling selective metal layers into openings such that one of the selective metal layers is overgrown over the surface of the insulating layer in the opening having a lower topology; forming a photoresist layer on the resulting structure; patterning the photoresist layer to expose the upper surface of the overgrown selective metal layer; removing the upper portion of the overgrown selective metal layer, such that the topology of the overgrown selective metal layers is the same as that of the non-overgrown selective metal layer; and forming a metal wiring connected to the selective metal layers.

Abstract: Semiconductor device and circuits and methods of fabrication which provides multilevel interconnections with grown diamond insulation films and second level resistors in the diamond insulation. The diamond provides both good electrical insulation and good thermal conductivity. The methods also provide capacitors with second level diamond dielectrics.

Abstract: A process to fabricate a specified height and cross-section of Microwave Monolithic Integrated Circuit gold posts comprising a patterned conductive substrate overlayed by an adhesive layer, a matrix layer, and a photoresist layer. Using photolithographic techniques, gold post locations are defined in the photoresist layer. m Gold post locations and cross-sections are defined in the matrix layer. The adhesive layer at the gold post locations is removed. The gold post locations are plated to form gold posts. The matrix is etched and the adhesive is dissolved.

Abstract: A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

Abstract: A method of forming a multi-layer interconnection is provided by which a resist pattern can be precisely formed by maintaining a uniform resist pattern film thickness and such problems as reduced electric resistance of a connecting portion and defective connection between a first interconnection layer and a second interconnection layer will not occur by ensuring a sufficient diameter of a contact hole. The method includes the steps of: removing a portion of an insulating layer having a main surface and covering a first conductive layer to form a hole reaching the first conductive layer in the insulating layer; forming an organic layer at least filling the hole; removing a portion of the insulating layer at a portion at which the insulating layer contacts an organic layer filling the hole; removing the organic layer filling the hole to form a recessed portion continuous to the hole in the insulating layer; and forming a second conductive layer in such a manner that it fills the hole and the recessed portion.

Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.