Abstract: A method for fabricating a semiconductor device includes the steps of forming an interconnect metal film on an insulating layer and forming, on a surface of the interconnect metal film, a first insulating film formed of P--SiN. The first insulating film and the interconnect metal film are simultaneously patterned to form a lower interconnect. On the resulting surface, a second insulating film having a polishing rate higher than that of the first insulating film is formed. The entire surface of the second insulating film is flattened by a chemical mechanical polishing process using the first insulating film as a stopper. Then, on the resulting surface, a third insulating film is formed. According to one embodiment, the first insulating film used as the stopper remains on the lower interconnect but not between adjacent interconnects and, according to another embodiment, such film is completely removed by etching.

Abstract: A first opening formed in a photo-resist layer is topographically covered with a spacer layer of silicon oxide so as to define a second opening narrower than the first opening, and the spacer layer and a target layer of silicon oxide therebeneath are anisotropically etched so as to form a contact hole narrower than the first opening in the target layer.

Abstract: An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out-diffusion of copper. A discontinuous film (30) of islands (41) is used to dope the interconnect structure (10)with copper. A conductive layer (14) is formed to fill a first portion (21) and a second portion (22) of the damascene structure (12). An anneal step is performed to diffuse the copper into the conductive layer (14).

Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: A method of manufacturing a semiconductor device having an insulating film includes the steps of: preparing a substrate having a step on a surface thereof; coating polysilazane on the surface of the substrate; and curing the polysilazane in a non-oxidizing atmosphere. Polysilazane coated on a substrate can be cured without corrosion and destruction of underlie wiring patterns.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A method for forming contact holes in a semiconductor device, involving formation of a ring-shaped pad at a contact region. The ring-shaped pad is used as an etch barrier film upon forming a contact hole. The use of such a ring-shaped pad enables easy formation of a contact hole with a critical dimension. In accordance with this method, it is possible to increase a process margin upon the formation of contact holes for providing contacts with a critical dimension while maintaining an insulation between neighboring conductors.

Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

Abstract: The invention provides a method and structure in which a nucleating species [54] is implanted through apertures [52] of a metal-phobic layer [40] into a support layer [17] and copper or a like metal is selectively grown at the implant site or sites. The implant support layer [17] is preferably composed of a material which inhibits diffusion therethrough of the copper or other like grown metal.

Abstract: A contact to a silicon semiconductor body is fabricated in a manner which merges the benefits of the low contact resistance provided by titanium silicide or cobalt silicide and the good step coverage provided by selective chemical vapor deposition (CVD) of tungsten or molybdenum from tungsten hexafluoride or molybdenum hexafluoride. An intermediate adhesion layer of molybdenum silicide or tungsten silicide is formed by physical vapor deposition, e.g., sputtering or vacuum evaporation, of molybdenum or titanium, followed by annealing. Such adhesion layer protects the underlying layer against damage by fluorine during CVD of the overlying layer of tungsten or molybdenum, as well as providing low resistance and good adhesion to both the underlying and overlying layers.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: There are disclosed a semiconductor device and a fabrication process thereof. The semiconductor device comprises a trench contact hole which goes through a source electrode of MOSFET to a semiconductor substrate, and a conductive wire filled in the trench contact hole. A substrate electrode is formed underneath the trench contact hole and thus, electrically connected with the source electrode by the conductive wire. Accordingly, the semiconductor device is very reduced in the connection part between the source electrode and the substrate electrode and can be applied for accomplishment of high integration of semiconductor device.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract: A method is provided of fabricating a semiconductor device having a wiring layer of a desired resistance component and capable of eliminating variation of wiring resistance by causing breakage of an Al or Al alloy layer of a laminated structure at certain positions. The multilayer conductive patterns of the invention include a laminate of a low melting point conductive layer formed of at least aluminum and a high melting point conductive layer. The side surfaces of the low melting point conductive layer includes recessed portions located at spaced apart length intervals of the multilayer conductive patterns.

Abstract: A semiconductor device has a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole. The semiconductor device is manufactured by a method that includes plasma etching at least one surface of the insulating interlayer the in an atmosphere having as a major component either a carbonless, chlorine-based gas or a carbonless, chlorine-based gas and an inactive gas in order to remove contaminates that would otherwise promote reactivity with aluminum CVD on the surface of the insulating interlayer.

Abstract: A method is provided for forming an improved landing pad with barrier of a semiconductor integrated circuit, and an integrated circuit formed according to the same. An opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a silicide layer disposed over a barrier layer which is disposed over a polysilicon layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. The barrier layer, formed as part of the landing pad, will provide for a uniform and high integrity barrier layer between the diffused region and an overlying aluminum contact to prevent junction spiking. A second dielectric having an opening therethrough is formed over the landing pad. A conductive contact, such as aluminum, is formed in the contact opening.

Abstract: The present invention is related to a method for forming a damage-free buried contact. The method according to the present invention includes steps of a) providing a silicon substrate; b) forming an oxide layer on the silicon substrate; c) forming a first conductive layer on the oxide layer; d) defining a buried contact region on the first conductive layer on the first conductive layer; e) removing a portion of the first conductive layer according to a shape of the buried contact region; f) implanting ions in the buried contact region to form an ion-implantation region under the oxide layer; and f) removing a portion of the oxide layer to obtain the buried contact. The step f) can be executed either before or after the step f). The present invention provides a method for forming a buried contact by which trench will not be occurred on the silicon substrate during the etching process thereof, so that a damage-free buried contact can be obtained.

Abstract: A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched into the first semiconductor substrate. A conductive material is deposited into the trenches. An insulating material is deposited over the surface of the substrate, polished and planarized. The bottom side of the first semiconductor substrate is ground, polished, and selectively etched so that the deep trenches form protrusions from the bottom surface. A passivation layer and a polyimide layer are deposited on the bottom surface of the first semiconductor substrate and etched away around the protrusions. A passivation layer and a polyimide layer are deposited over the top surface of the second semiconductor substrate.