Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: A transparent display substrate and a driving method thereof, and a transparent display device are provided. The transparent display substrate includes a base substrate and pixel units which are located above the base substrate and arranged in an array, each of the pixel units comprises a display region and a transparent region; a first light emitting layer is provided in the transparent region, and a first electrode is provided at a side of the first light emitting layer proximal to the base substrate and a second electrode is provided at a side of the first light emitting layer distal to the base substrate; a brightness of light emitted by the first light emitting layer is adjusted according to change in a difference between a first voltage and a second voltage loaded on the first electrode and the second electrode, respectively.

Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, and a gate electrode. The source region and the drain region are in the substrate, and the gate electrode is partly buried in the substrate and between the source region and the drain region.

Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.

Abstract: A semiconductor memory device includes a substrate defined with a cell array region and a connection region which extends in a first direction from the cell array region; an electrode structure including a bottom electrode structure which includes plurality of bottom electrodes stacked on the substrate to be separated from one another and a top electrode structure which includes plurality of top electrodes stacked on the bottom electrode structure to be separated from one another and has a stepped structure which includes plurality of stepping surfaces, in the connection region; and plurality of recess holes formed to a first depth from stepping surfaces of the stepped structure, and having bottom surfaces which expose the bottom electrode structure, wherein the first depth is substantially same as a height of the top electrode structure, and distances of the bottom surfaces of the recess holes from the substrate are different from one another.

Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.

Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.

Abstract: An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.

Abstract: An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus.

Abstract: A display device including a substrate including: a top surface, a bottom surface, and a plurality of side surfaces connecting the top surface and the bottom surface; a signal line disposed on the top surface; a sidewall electrode in electrical contact with the signal line and disposed on a first side surface of the side surfaces; and a connection electrode in electrical contact with the sidewall electrode and disposed on the first side surface.

Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.

Abstract: The present application discloses a semiconductor device structure and a method for forming the same. The method includes forming a pillar over a substrate, forming a first ring structure over a sidewall of the pillar, removing the pillar to form a first opening surrounded by the first ring structure, forming a second ring structure in the first opening, forming a third ring structure surrounding the first ring structure after the first opening is formed, and removing the first ring structure to form a gap between the second and third ring structures. A semiconductor device structure includes a dielectric layer over a substrate, a first ring structure over the dielectric layer, and a second ring structure over the dielectric layer and surrounding the first ring structure, wherein the first and the second ring structures have a first common center.

Abstract: Methods and apparatus for forming a magnetic tunnel element are provided herein. A method of forming a magnetic tunnel element includes: depositing a magnetic layer atop a cobalt-chromium seed layer; and depositing a tunnel layer atop the magnetic layer to form a magnetic tunnel element, wherein the magnetic tunnel element has a TMR greater than 100. For example, a cobalt/platinum material or one or more layers thereof may be deposited directly atop a cobalt-chromium seed layer to produce improved devices.