Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: A leadframe includes a common contact. A first transistor is disposed over the leadframe with a first interconnect structure of the first transistor disposed over the common contact. A second transistor is disposed over the leadframe with a second interconnect structure of the second transistor disposed over the common contact.

Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: A dual sided contact switch has a first independent drain/source region of a multi-gate active device. The dual sided contact switch also has a first shared drain/source region of the multi-gate active device. The dual sided contact switch has a second independent drain/source region of the multi-gate active device, adjacent to the first shared drain/source region. The dual sided contact switch also has a second shared drain/source region of the multi-gate active device, adjacent to the first independent drain/source region. The dual sided contact switch has a gate region between the first independent drain/source region and the first shared drain/source region, and also between the second independent drain/source region and the second shared drain/source region.

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

Abstract: The present invention provides complexes of the formula (L)M(X), in which M is a metal atom selected from copper, silver and gold; L is a carbene ligand; and X is a monoanionic ligand. The complexes are useful as light emitters in the emissive zone of light-emitting devices such as OLEDs. The present invention also provides organometallic complexes which exhibit RASI photoemission, and the use of the same in light-emitting devices such as OLEDs.

Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.

Abstract: An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

Abstract: According to one embodiment, a semiconductor device includes a first gate electrode, a semiconductor layer, a first insulating layer, a second gate electrode, a second insulating layer, a third insulating layer, a first contact hole, and a first electrode. The first electrode passes through the first contact hole and electrically connects the first gate electrode, the first region and the second gate electrode.

Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.