Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.

Abstract: A detection panel and a manufacturing method of the same are provided. The detection panel includes: a photosensitive element configured to sense a first light beam incident to the photosensitive element to generate a photosensitive signal; a drive circuit configured to be coupled to the photosensitive element to acquire the photosensitive signal from the photosensitive element, the drive circuit including a switch element; and a reflective grating which is on a side of the drive circuit where the first light beam is incident, and is configured to reflect at least a portion of the first light beam incident toward the switch element.

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A fabrication method for a flexible bifacial dye-sensitized solar cell is described. The method involves forming a flexible counter electrode of crystalline Pt nanoparticles on a first conductive layer by irradiating a precursor solution with a UV lamp. A flexible photoanode is formed by applying metal oxide particles to a second conductive layer, and then the solar cell is constructed by sandwiching an electrolyte between the counter electrode and photoanode.

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

Abstract: The present invention relates to a chemically amplified photoresist composition including an alkali-soluble resin and a polymeric photo-acid generator having a predetermined structure, a photoresist pattern produced from the chemically amplified photoresist composition, and a method for preparing the chemically amplified photoresist pattern.

Abstract: Provided are: a curable composition having excellent photolithographic properties and resin elution properties; a cured product of the curable composition; and a curing method of the curable composition. The curable composition is characterized by including: (A) at least one selected from the group consisting of a water-soluble polyfunctional (meth)acrylates and water-soluble polyfunctional (meth)acrylamides; and (B) a photosensitive group-containing water-soluble polymer. The water-soluble polyfunctional (meth)acrylates are preferably compounds represented by Formula (I) below, and the water-soluble polyfunctional (meth)acrylamides are preferably compounds represented by Formula (II) below.

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

Abstract: In one embodiment, a guide layout creating apparatus includes a selection module that selects a first point as a point on which a guide to array a plurality of particles in a first array is arranged. The apparatus further includes a calculation module that calculates first free energy when the plurality of particles are arrayed in the first array by the guide arranged on the first point, and second free energy when the plurality of particles are arrayed in a second array by the guide arranged on the first point, a type of the second array being different from a type of the first array. The apparatus further includes a determination module that determines whether the first point is employed as the point on which the guide is arranged on the basis of the first free energy and the second free energy.

Abstract: A photoacid generator having formula (1a) is provided. A chemically amplified resist composition comprising the PAG forms a pattern of rectangular profile with a good balance of sensitivity and LWR when processed by photolithography using ArF excimer laser, EB or EUV.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: A chemically amplified positive-type photosensitive resin composition containing a predetermined amount of organic solvent (S1) having a boiling point of 120 to 180° C., and satisfying the following requirements: a solvent residual rate measured by the following steps (1) and (2) is 3.5% by mass or less: (1) forming a coated film of 40 ?m by applying the photosensitive resin composition to a substrate; and (2) baking the coated film at a temperature that is higher by 10° C. than the boiling point of the organic solvent (S1) for 30 seconds, and calculating the rate of the organic solvent (S1) in a total mass of the coated film after baking by gas chromatography.

Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.

Abstract: A transparent display substrate and a driving method thereof, and a transparent display device are provided. The transparent display substrate includes a base substrate and pixel units which are located above the base substrate and arranged in an array, each of the pixel units comprises a display region and a transparent region; a first light emitting layer is provided in the transparent region, and a first electrode is provided at a side of the first light emitting layer proximal to the base substrate and a second electrode is provided at a side of the first light emitting layer distal to the base substrate; a brightness of light emitted by the first light emitting layer is adjusted according to change in a difference between a first voltage and a second voltage loaded on the first electrode and the second electrode, respectively.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, and a gate electrode. The source region and the drain region are in the substrate, and the gate electrode is partly buried in the substrate and between the source region and the drain region.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.