Abstract: A light-emitting device includes a base member, conductor wiring on an upper surface of the base member, a reflective member covering the upper surfaces of the base member and the conductor wiring and having apertures to expose part of the upper surface of the base member and part of the upper surface of the conductor wiring, a plurality of light sources bonded to the part of the upper surface of the conductor wiring located in the apertures with bonding members, and a reflector that is disposed on the reflective member and includes a plurality of first surrounding portions and a plurality of second surrounding portions surrounding the first surrounding portions, which respectively surround the light sources in a plan view. Each surrounding portion has inclined lateral surfaces that widen in an upward direction. An aperture in each second surrounding portion is smaller than an aperture in each first surrounding portion in the plan view.

Abstract: A display device and a method of manufacturing the same are provided. A display device includes: a display panel including a first area, a second area, and a bending area between the first area and the second area; a first polarizing film on a first surface of the first area of the display panel; and a second polarizing film on a first surface of the second area of the display panel, and the first and second polarizing films are spaced apart from each other with the bending area therebetween.

Abstract: A display device includes a substrate including a first substrate portion including a first area, a second substrate portion including a second area, and a bending area between the first substrate portion and the second substrate portion, the substrate being bendable around a bending axis that extends in a first direction, an encapsulation portion over the first substrate portion, a seal portion between the first substrate portion and the encapsulation portion to bond the first substrate portion to the encapsulation portion, an intermediate wiring including a first intermediate wiring portion in the first area and a second intermediate wiring portion in the second area, the intermediate wiring being covered by at least one inorganic layer, and a connection wiring including at least a portion in the bending area and connecting the first intermediate wiring portion to the second intermediate wiring portion.

Abstract: A method of making an energy storage article having a metal nitride electrode is disclosed where metal nitride is made by nitriding particles of a metal or oxide of a metal selected from vanadium molybdenum, titanium, niobium, tungsten, or combinations including any of the foregoing by contacting the particles with a gas of nitrogen and hydrogen, or ammonia, in a fluidized bed reactor to form particles of metal nitride for the electrode.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate having a pattern-dense region and a pattern-loose region; a first drain stressor disposed in the pattern-dense region; a first source stressor disposed in the pattern-dense region; a buried gate structure disposed in the pattern-dense region, between the first drain stressor and the first source stressor; a second drain stressor disposed in the pattern-loose region; a second source stressor disposed in the pattern-loose region; and a planar gate structure disposed in the pattern-loose region, between the second drain stressor and the second source stressor.

Abstract: A semiconductor device includes a substrate, a nanotube structure, and a gate structure. The nanotube structure is disposed over the substrate. The nanotube structure includes a semiconducting carbon nanotube (s-CNT) and a first insulating nanotube. The first insulating nanotube has an inert surface on the s-CNT. The gate structure includes a first metallic carbon nanotube (m-CNT) over the nanotube structure.

Abstract: Light emitting diode (LED) packages and LED displays utilizing the LED packages are disclosed. LED packages can have a plurality of cavities with each having one or more LEDs. The LEDs can be individually controllable so that the LED package emits the desired color combination of light from the package. The LED packages are arranged with an encapsulant over the cavities that shape the LED package emission to a wide angle or pitch. Some of the LED packages can have three cavities, while others can have four or more cavities. The packages can comprise an encapsulant that forms lenses over the cavities and continues beyond the cavities to cover surfaces of the LED package body. The body can include different anchoring features to improve package reliability by anchoring the encapsulant to the body. One embodiment of an LED display according to the present invention comprises a plurality of LED packages, at least some having a plurality of cavities.

Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.

Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.

Abstract: A magnetic memory array having a source-plane electrically connected with an array of channel selectors in two-dimensions. The array of channel selectors can be arranged in rows and columns with both the rows and columns being electrically connected with a source-plane. A memory element such as a two terminal resistive switching memory element can be electrically connected with each of the channel selectors. The source-plane can include a doped region formed in a surface of a semiconductor substrate and may also include an electrically conductive layer formed on the doped region. The use of such a planar, two-dimensional source-plane allows for greatly increased data density by eliminating the need to form separate source-line source lines for individual rows of channel selectors.

Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Abstract: Lighting modules and methods of manufacturing the same. The lighting module described herein may include a flexible printed circuit board substrate, light emitting diodes mounted on one side of the printed circuit board substrate, and thermally-conductive substrate plates opposite of the light emitting diodes to provide structural support and thermal management.

Abstract: Provided are a magnetic tunnel junction device and a magnetic resistance memory device which are capable of both reducing a write current and increasing a write speed. The magnetic tunnel junction device includes a free layer having a first magnetization direction that is changeable, a pinned layer that is configured to maintain a second magnetization direction in a predetermined direction, and an insulating layer between the free layer and the pinned layer. The free layer includes a first free layer having perpendicular magnetic anisotropy and high polarizability, and a second free layer that is antiferromagnetic-coupled to the first free layer.

Abstract: There is provided a technique that includes: (a) forming a silicon germanium film in an amorphous state so as to embed an inside of a recess formed on a surface of a substrate, by supplying a first silicon-containing gas and a germanium-containing gas to the substrate at a first temperature; (b) raising a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature; and (c) forming a silicon film on the silicon germanium film by supplying a second silicon-containing gas to the substrate at the second temperature, wherein in (c), the silicon germanium film as a base of the silicon film is crystallized while the silicon film is formed.

Abstract: A magnetic memory array having a source-plane electrically connected with an array of channel selectors in two-dimensions. The array of channel selectors can be arranged in rows and columns with both the rows and columns being electrically connected with a source-plane. A magnetic memory element such as a magnetic tunnel junction element can be electrically connected with each of the channel selectors. The source-plane can include a doped region formed in a surface of a semiconductor substrate and may also include an electrically conductive layer formed on the doped region. The use of such a planar, two-dimensional source-plane allows for greatly increased data density by eliminating the need to form separate source-line source lines for individual rows of channel selectors.

Abstract: An image sensor is provided comprising a substrate comprising first and second surfaces opposite to each other. A first isolation layer is disposed on the substrate and forms a boundary of a sensing region. A second isolation layer is disposed at least partially in the substrate within the sensing region and has a closed line shape. A photoelectric conversion device is disposed within the closed line shape of the second isolation layer, and a color filter is disposed on the first surface of the substrate.