Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

Abstract: A method of making a structure having a patterned a base layer and useful in the fabrication of optical and electronic devices including bioelectronic devices includes, in one embodiment, the steps of: a) providing a layer of a radiation-sensitive resin; b) exposing the layer of radiation-sensitive resin to patterned radiation to form a base layer precursor having a first pattern of exposed radiation-sensitive resin and a second pattern of unexposed radiation-sensitive resin; c) providing a layer of fluoropolymer in a third pattern over the base layer precursor to form a first intermediate structure; d) treating the first intermediate structure to form a second intermediate structure; and e) selectively removing either the first or second pattern of resin by contacting the second intermediate structure with a resin developing agent, thereby forming the patterned base layer.

Abstract: The invention relates to a method for producing a thermoelectric component or at least a semifinished version thereof, in which at least one thermoelectric active material in dry powder form is introduced into at least some of the holes of a perforated template. It addresses the problem of specifying a method which can be conducted in a particularly economically viable manner. The problem is solved by virtue of the active material remaining in the holes of the template, and the template filled with active material becoming a constituent of the thermoelectric component produced.

Abstract: The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved.

Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.

Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.

Abstract: Approaches herein provide precise areal surface reaction with directional ion beam activation. Exemplary approaches include selectively forming a material within a trench of a semiconductor device using a plurality of successive deposition and activation cycles. Each of the plurality of deposition and activation cycles includes forming a precursor conformally along a set of surfaces of the trench, reacting the precursor with a capping compound to form a capping layer along the set of surfaces of the trench, and performing an ion implant to the semiconductor device to activate just a portion of the capping layer. In one approach, the ion implant activates just a portion of the capping layer along a bottom surface of the trench. In another approach, the ion implant activates just a portion of the capping layer along an upper section of a sidewall of the trench.

Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method for cleaning a base for supporting an object to process in an apparatus configured to perform a heat process, the method comprising a first step of forming an oxide film on the base including silicon carbide, by subjecting the base to a heat process in a gas atmosphere including oxygen, and a second step of, after the first step, subjecting the base to a heat process in a gas atmosphere including steam, wherein the first step is performed for 10 hours at a temperature of 1000° C. or more.

Abstract: A method includes receiving a wafer stack having at least two wafers bonded together. At least one blade is inserted between a first wafer of the at least two wafers and a second wafer of the at least two wafers. The blade has a channel configured to inject air or fluid. The first wafer is debonded from the second wafer using the at least one blade. In another embodiment, a detacher having a convex bottom surface is attached to the wafer stack. The first wafer is debonded from the second wafer using the detacher.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

Abstract: An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process.

Abstract: Methods of repairing damaged low-k dielectric films using UV-activated photosensitive organic compounds are described herein. Methods of sealing pores by exposing porous dielectric films to UV-activated large photosensitive organic compounds are also described. Methods also include mechanically reinforcing dielectric films using photosensitive organic compounds activated by UV radiation. Compounds include at least one photosensitive end group, such as an unsaturated bond or group with high ring strain.

Abstract: A polish apparatus including a rotatable table configured to receive a polish pad having a polish surface; a polish head configured to hold a polish object and configured to be capable of placing the polish object in contact with the polish surface while holding the polish object; at least one contact portion being provided with a contact surface and configured to be capable of contacting the polish surface when the table is in rotation; and a measurement portion configured to measure a state of the contact surface of the contact portion being configured to contact the polish surface of the polish pad.

Abstract: The invention relates to a method and a device for coating surfaces of a substrate (8) according to the technique of plasma-assisted chemical vapor deposition. The basic idea of the present invention is to increase the ion concentration prevailing in the plasma so as to have more ions accumulate on the substrate (8) and to promote layer growth (12). According to the invention, the ion concentration is increased by forming a so-called fireball at the surface of the substrate (8) to be coated. The term fireball refers to the ionization processes that occur on electrode surfaces (2) as spontaneous small brightly luminescent phenomena in plasma processes. To this end, an electrode (2) is introduced into an existing background plasma and connected to a positive potential (4).

Abstract: A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die.

Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Abstract: The disclosure relates to a method for making an epitaxial structure. A carbon nanotube film is placed on an epitaxial growth surface of a substrate. The carbon nanotube film defines a number of apertures so that part of the epitaxial growth surface is exposed from the apertures to form a first exposed part. A mask preform layer is deposited on the epitaxial growth surface to cover the carbon nanotube film. A thickness of the mask preform layer is smaller than a thickness of the carbon nanotube film so that a first part of the mask preform layer is deposited on surfaces of the carbon nanotube film and a second part of the mask preform layer is deposited on the first exposed part of the epitaxial growth surface. The carbon nanotube film is removed. An epitaxial layer is grown on the epitaxial growth surface.

Abstract: Method and apparatus for characterizing metal oxide reduction using metal oxide films formed in an anneal chamber are disclosed. Oxygen is provided into an anneal chamber. A substrate including a metal seed layer is exposed to the oxygen and exposed to a heated substrate support in the anneal chamber to form a metal oxide of the metal seed layer. The oxidized substrate can be stored for later use or transferred to a processing chamber for reducing the metal oxide to metal. The oxidized substrates formed in this manner provide metal oxides that are repeatable, uniform, and stable. The oxidized substrate is exposed to a reducing treatment under conditions that reduce the metal oxide to metal in the form of a film integrated with the metal seed layer.