Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface inclined with respect to a {000-1} face at an angle of 0° to 10° or a surface a normal line direction of which is inclined with respect to a <000-1> direction at an angle of 80° to 90°, a gate electrode, an insulating layer at least a part of which is provided between the surface and the gate electrode, and a region, at least apart of which is provided between the surface and the insulating layer, including a bond between carbon and carbon.

Abstract: Disclosed herein is a wafer processing method in which laser processing is carried out on a wafer along streets. The wafer processing method includes a step of holding the wafer by a chuck table, a protective film forming step of forming a water-soluble protective film on a surface of the wafer, a laser beam irradiating step of irradiating the wafer with a laser beam along the streets after the protective film forming step, a step of supplying a chemical having an amino group to the wafer, and a removing step of cleaning and removing a compound that is generated by the supplying of the chemical having an amino group and contains phosphorus.

Abstract: An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold a top surface of the substrate stack, and at least one blade configured to be inserted between two adjacent substrates of the substrate stack, wherein the at least one blade has a pointed tip in plan view and has a channel configured to inject air or fluid.

Abstract: A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire.

Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.

Abstract: In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.

Abstract: [Problem] To provide a highly heat resistant resin composition which exhibits good tackiness at low temperatures less than or equal to 180° C., and whose production of a volatile portion due to decomposition or the like is small even at high temperatures greater than or equal to 250° C., and whose increase in adhesive force is small even after passage through a heat treatment step, and therefore which allows a base material to be easily peeled off at room temperature when the base material is to be peeled off, and a cured membrane and a laminate film that employ this resin composition.

Abstract: The present invention increases controllability of a composition ratio of a multi-element film that contains a predetermined element and at least one element selected from the group consisting of boron, oxygen, carbon and nitrogen. There is provided a method of manufacturing a semiconductor device, including: forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming the first film being free of borazine ring structure and including a predetermined element and at least one element selected from the group consisting of oxygen, carbon and nitrogen; and (b) forming the second film having a borazine ring structure and including at least boron and nitrogen.

Abstract: A semiconductor device includes a cooling plate made of metal, one or more laminated substrates each formed by laminating a circuit board, an insulating board, and a metal board, and one or more first semiconductor elements each made of a wide-band-gap semiconductor and disposed over outer peripheral edge portions of the circuit board. The metal board and the cooling plate are joined by the use of a joining material. As a result, even if temperature rises due to the operation of the one or more first semiconductor elements and heat radiation is not performed properly, the one or more first semiconductor elements operate stably.

Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.

Abstract: A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region.

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

Abstract: An electronic device, suitable for achieving a smaller size, includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a main electronic element arranged on the substrate, and a conducting layer electrically connected to the main electronic element. The substrate is formed with an element arrangement recessed portion that is recessed from the main surface and in which the main electronic element is arranged. The element arrangement recessed portion has a bottom surface facing in the thickness direction, and a side surface inclined with respect to the thickness direction of the substrate. The electronic device includes an auxiliary electronic element formed on the side surface of the element arrangement recessed portion.

Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.