Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

Abstract: There is provided a cleaning technique that includes supplying a hydrogen fluoride gas into a process vessel, in which a process of forming an oxide film containing at least one of carbon and nitrogen on a substrate has been performed, to remove a deposit containing at least one of carbon and nitrogen adhered to an interior of the process vessel, wherein the act of supplying the hydrogen fluoride gas is performed under a condition in which an etching rate of the deposit adhered to the interior of the process vessel is higher than an etching rate of a quartz member in the process vessel.

Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.

Abstract: A display includes a display panel and a first protection sheet. The display panel has flexibility and a light output face. The first protection sheet is provided on the light output face and includes a first shock dispersion layer, a first strain relaxation layer, and a first shock absorption layer. The first shock dispersion layer includes a flexible reinforced-glass member, a flexible hard-coat film, or a flexible double-sided hard-coat film. The first strain relaxation layer includes a wet-laminated layer or a dry-laminated layer that is in close contact with a surface of the first shock dispersion layer adjacent to the display panel. The first shock absorption layer includes a gel layer having a thickness of submillimeter order or greater. The first shock absorption layer, the first strain relaxation layer, and the first shock dispersion layer are laminated in this order from the light output face of the display panel.

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.

Abstract: A gate electrode is formed in a trench formed in a semiconductor substrate. A gate interlayer insulating film is formed to cover the gate electrode and the like. A gate interconnection and an emitter electrode are formed in contact with the gate interlayer insulating film. A glass coating film and a polyimide film are formed to cover the gate interconnection and the emitter electrode. A solder layer is formed to cover the polyimide film. The gate interconnection and the emitter electrode are each formed of a tungsten film, for example.

Abstract: Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.

Abstract: A transient electronic device includes electronic elements (e.g., an SOI- or chip-based IC) and a trigger mechanism disposed on a frangible glass substrate. The trigger mechanism includes a switch that initiates a large trigger current through a self-limiting resistive element in response to a received trigger signal. The self-limiting resistive element includes a resistor portion that generates heat in response to the trigger current, thereby rapidly increasing the temperature of a localized (small) region of the frangible glass substrate, and a current limiting portion (e.g., a fuse) that self-limits (terminates) the trigger current after a predetermined amount of time, causing the localized region to rapidly cool down.

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: A pre-processing method, a method for forming a metal silicide and a semiconductor processing apparatus are disclosed by the present invention. In the pre-processing method, a plasma etching process is performed on a semiconductor structure including a substrate. A first conductive portion and an isolation spacer covering a side surface of the first conductive portion are formed on a surface of an active area in the substrate. In the plasma etching process, a bias voltage applied to a surface of the semiconductor structure is adjusted by adjusting power outputs of two RF sources and is not lower than 150 V. In the metal silicide formation method, after a semiconductor structure including a first conductive portion and a second conductive portion is pre-processed in the manner as described above, a metal film is deposited thereon and annealed to result in the formation of the metal silicide.

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

Abstract: Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a pixel region in which a plurality of pixels is disposed; a surrounding region provided around the pixel region; an organic photoelectric conversion layer continuously provided from the pixel region to a portion of the surrounding region; an electrically-conducive layer provided on the organic photoelectric conversion layer from a periphery of the pixel region to the surrounding region; and a black layer provided on the electrically-conducive layer. The electrically-conducive layer has a light-shielding property.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor memory device according to the embodiments includes a first laminated body, a second laminated body, an intermediate insulation layer, and a columnar body. The intermediate insulation layer is positioned between the first laminated body and the second laminated body. A plurality of conductive layers of the second laminated body include a first conductive layer which is positioned closest to the intermediate insulation layer among the plurality of conductive layers of the second laminated body. The first conductive layer has a main body part having a first end surface facing the columnar body, and a protrusion part which protrudes from the main body part to the first laminated body, and has a second end surface facing the columnar body. The first end surface and the second end surface are continuous with each other.

Abstract: Provided is a display device. The display device includes a first substrate including a first base layer, a circuit layer disposed on the first base layer, and a light emitting layer disposed on the circuit layer, a second substrate including a top surface and a bottom surface and in which a plurality of grooves arranged in a first direction are defined in the bottom surface, the second substrate being disposed on the first substrate, and a plurality of light blocking members disposed on the plurality of grooves to control propagation direction of light outputted from the light emitting layer.