Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

Abstract: A flexible and stretchable imager includes a first rigid substrate carrying at least one first photodetector, a second rigid substrate carrying at least one second photodetector, and a flexible and stretchable arm connected to the first and second rigid substrates. The first rigid substrate, the second rigid substrate, and the flexible and stretchable arm are made of a same material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

Abstract: An optical sensor module includes a first frame set, a second frame set and a housing which partially covers the first frame set and the second frame set. The first frame set has a first chip-mounting frame and a first wiring frame. The first chip-mounting frame has a first chip-mounting section, and a first conductive lead. At least one first indentation is formed on the first chip-mounting section. The second frame set has a second chip-mounting frame and a second wiring frame. The second chip-mounting frame has a second chip-mounting section and a second conductive lead. At least one second indentation is formed on the second chip-mounting section.

Abstract: A method of manufacturing a semiconductor memory includes: forming a first lamination on a substrate; forming a first hole through the first lamination; embedding a first sacrificial material including a thermally decomposable organic material in the first hole; forming a recess at an upper portion of the first hole; forming an oxide film in the recess; removing the first sacrificial material under the oxide film; embedding a second sacrificial material on the oxide film in the recess; forming a second lamination on the first lamination and the second sacrificial material; forming a second hole through the second lamination at a position corresponding to the first hole by etching the second lamination in an extension direction of the first hole; and removing the oxide film and the second sacrificial material.

Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.

Abstract: The present disclosure provides an ultra-high color rendering white light-emitting device including a semiconductor LED chip that emits a violet wavelength range of light with an emission peak at 380 nm to 430 nm, and a phosphor layer distributed in a transparent resin layer that emits light when excited by an excitation wavelength of the violet LED chip, wherein the phosphor layer includes a first phosphor having an emission peak at 450-470 nm, a second phosphor having an emission peak at 510-550 nm, a third phosphor having an emission peak at 550-590 nm, a fourth phosphor having an emission peak at 630-660 nm, and a fifth phosphor having an emission peak at 660-730 nm, and the ultra-high color rendering white light-emitting device has Ra that is equal to or higher than 98 and less than 100.

Abstract: The invention relates to a method for manufacturing at least one passivated planar photodiode 1, comprising the following steps: producing a semiconductor detection portion 10; depositing a dielectric passivation layer 20; producing a peripheral portion 21 made from a doped semiconductor material; diffusion-annealing the doping elements from the peripheral portion 21 into the semiconductor detection portion 10, forming a doped peripheral region 14; producing a doped upper region 11, surrounded by the doped peripheral region 14.

Abstract: The present technology relates to a solid state imaging sensor that is possible to suppress the reflection of incident light with a wide wavelength band. A reflectance adjusting layer is provided on the substrate in an incident direction of the incident light with respect to the substrate such as Si and configured to adjust reflection of the incident light on the substrate. The reflectance adjusting layer includes a first layer formed on the substrate and a second layer formed on the first layer. The first layer includes a concavo-convex structure provided on the substrate and a material which is filled into a concave portion of the concavo-convex structure and has a refractive index lower than that of the substrate, and the second layer includes a material having a refractive index lower than that of the first layer. It is possible to reduce the reflection on the substrate such as Si by using the principle of the interference of the thin film. Such a technology can be applied to solid state imaging sensors.

Abstract: The present invention provides a method for detecting an ultra-small defect on a wafer surface, film layer having ultra-small defect that causes abnormalities on the surface of the film layer; form a photoresist pattern with a pattern defect; etching the film layer according to the photoresist pattern to form a film layer pattern with an enlarged defect; and scanning the film layer pattern by using a defect scanner to capture the enlarged defect. In this method, enlarging the size of the ultra-fine particle defect through the exposure defocusing principle; or by adding the photomask consisting of the repeating units, using the repetition pattern as the exposure pattern and combing with the repeating cell to cell comparison method, the capture ability of the detection machine is further improved. Therefore, it can be detected by amplifying the defects of ultrafine particles which cannot be detected by conventional methods.

Abstract: Embodiments of an improved light-direction detection (LDD) device are described herein. The LDD device includes a substrate and at least one predefined structure formed along the substrate by stacking metal layers, contacts, and vias available in the manufacturing process of the device. The predefined structure is formed along a photodiode pair to collectively define an optical sensor configured to detect direction of incident light without need for off-chip components. The device accommodates light direction detection in two or more orthogonal planes.

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

Abstract: A variable capacitance element is provided that includes a plurality of resistance elements that form a path for applying a control voltage to the electrodes of a plurality of variable capacitance portions connected in series. These resistance elements include first distribution resistance elements, second distribution resistance elements, a first shared resistance element, and a second shared resistance element. Moreover, vertical sectional areas of the first shared resistance element and the second shared resistance element with respect to conducting directions thereof are larger than the vertical sectional areas of the first distribution resistance elements and the second distribution resistance elements with respect to conducting directions thereof.

Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.