Abstract: A mounting structure includes a semiconductor device including a first terminal, a wiring substrate including a second terminal having a first end, a wiring extracted from an end face of the first end, and a photosensitive insulating film that covers the wiring and the first end, the second terminal being disposed facing the first terminal, and a bump that electrically connects the first terminal and the second terminal.

Abstract: A LED leadframe for securing a LED chip includes a metallic base and an insulating layer. The metallic base includes a die bonding region and a peripheral region surrounding the die bonding region, and the die bonding region is for securing the LED chip. The insulating layer is disposed on the metallic base and located in the peripheral region to define the die bonding region. The insulating layer includes a bar-shaped insulating section disposed in the metallic base and corresponding to the die bonding region. The metallic base includes a first groove(s) defined corresponding to the die bonding region. The first groove(s) is/are filled with a thermally conductive filler. The invention improves the LED leadframe to allow heat conducting efficiencies of various regions of the base to be controllable and adjustable so as to reduce temperature differences among various regions of the base and thereby unify the temperature.

Abstract: A method for manufacturing the array substrate includes: forming a gate metal layer on a base by a first patterning process and forming a gate insulating layer on the gate metal layer; forming a semiconductor layer and a source/drain metal layer by a second patterning process on the resulted base, the source/drain metal layer including a data line and a metal electrode connected to the data line; forming a first electrode on the resulted base and forming a channel region by a third patterning process, the channel region causing the metal electrode to form a source electrode and a drain electrode; forming a passivation layer and an organic insulating layer by a fourth patterning process on the resulted base; the organic insulating layer at least corresponding to the data line; and forming a second electrode by a fifth patterning process on the resulted base.

Abstract: A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.

Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.

Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.

Abstract: A semiconductor device and method of manufacturing are provided. The semiconductor device includes a substrate; first and second structures spaced apart from each other on the substrate in a first direction, the first structure including a first lower electrode and the second structure including a second lower electrode; a first supporter pattern disposed on the substrate to support the first and second structures, and including a first region that exposes portions of sidewalls of the first and second structures, and a second region that covers a second portion of the sidewalls; and a second supporter pattern disposed on the first supporter pattern to support the first and second structures, the second supporter pattern including a third region, the third region configured to expose portions of the first sidewall and the second sidewall, and a fourth region that covers a portion of the first and second sidewalls.

Abstract: An aspect of the present disclosures is a method that includes applying a perovskite precursor solution to a first solid conductor and treating the perovskite precursor solution such that a first portion of the perovskite precursor solution is converted to a first solid perovskite, where the first solid conductor comprises a first charge transport characteristic, which is predominantly p-type or predominantly n-type, and the treating results in the first solid perovskite having a second charge transport characteristic that is substantially the same as the first charge transport characteristic.

Abstract: A method includes receiving a semiconductor wafer into a chamber; generating a plasma within the chamber to accelerate particles toward the semiconductor wafer; generating a magnetic field above the semiconductor wafer by an electromagnetic structure contained within the chamber, wherein the electromagnetic structure comprises a plurality of electromagnetic elements; and adjusting the magnetic field, wherein the adjusting of the magnetic field includes moving positions of each of the plurality of electromagnetic elements independently.

Abstract: A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: A semiconductor substrate according to the present invention includes a nitride semiconductor layer 203, an amorphous semiconductor layer 205 formed on one main surface side of the nitride semiconductor layer 203, a high-roughness layer 206 which is a semiconductor layer formed on the amorphous semiconductor layer 205 and has a surface roughness larger than the amorphous semiconductor layer 205, and a diamond layer 207 formed on the high-roughness layer 206. Damage to the nitride semiconductor layer can be reduced in forming the diamond layer on the nitride semiconductor layer and adhesion between the layers can be increased.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: A semiconductor device manufacturing method includes: a pretreatment step of performing a hydrophobic treatment on a first exposed region of an exposed surface, an n-type semiconductor layer being exposed from the first exposed region, and a pn junction being exposed from the exposed surface; an impurity supplying step of supplying an n-type impurity to the first exposed region; a channel stopper forming step of irradiating the first exposed region with a laser beam to introduce the n-type impurity into the n-type semiconductor layer, thus forming a channel stopper; and a glass layer forming step of forming a glass layer using a glass composition so as to cover the exposed surface.

Abstract: The present disclosure discloses a flexible display panel and a flexible display. The flexible display panel includes a flexible substrate with at least one bendable side, the flexible substrate comprises a display area and a drive controller, the flexible display panel of the present disclosure adjusts the aspect ratio by changing the structure of the drive controller, thereby shortening the length of the drive controller along the direction parallel to the bend line in the bend area, effectively avoiding defects of the structure of the drive controller on the flexible display panel, also increasing the viewing angle. In addition, in order to save the space, the flexible substrate connected to the drive controller is bent to the other side of the flexible substrate to make the drive controller drive the light emission of the display panel, which greatly reduces the volume of the flexible panel.

Abstract: In conventional solar cells with metal contacts, a non-negligible fraction of the incoming solar power is immediately lost either through absorption or reflection upon interaction with the contacts. Effectively transparent contacts (“ETCs”) for solar cells can be referred to as three-dimensional contacts designed to redirect incoming light onto a photoabsorbing surface of a solar cell. In many embodiments, the ETCs have triangular cross-sections. Such ETCs can be placed on a photoabsorbing surface such that at least one of their sides forms an angle with the photoabsorbing surface. In this configuration, the ETCs can redirect incident light onto the photoabsorbing surface, mitigating or eliminating reflection loss compared to conventional solar cells. When constructed in accordance with a number of embodiments of the invention, ETCs can be effectively transparent and highly conductive.

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

Abstract: The present disclosure discloses an array substrate, a display panel, and a display apparatus. The array substrate includes a first signal line and a second signal line as well as a first TFT and a second TFT electrically connected to the first signal line and the second signal line. The first TFT has a gate located on its first conductive layer, a source located on its second conductive layer which is connected to the first conductive layer through a first via hole, and a drain located on a fourth conductive layer of the second TFT. The second TFT has a gate located on its third conductive layer, a drain located on the second conductive layer of the first TFT, and a source located on its fourth conductive layer which is connected to the third conductive layer through a second via hole.