Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

Abstract: A method of operating a data storage device includes fetching a first plurality of commands from at least one submission queue generated in a host memory, determining whether a ratio of a second plurality of commands from among the fetched first plurality of commands exceeds a reference ratio, and adjusting a number of a plurality of pointers being fetched at substantially a same time based on determining whether the ratio exceeds the reference ratio. The second plurality of commands has a same property, the plurality of pointers indicates a physical address of the host memory corresponding to the first plurality of commands, and the data storage device includes a storage controller configured to perform an interfacing operation with a host including the host memory.

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.

Abstract: A method for cleaning files stored in a mobile terminal is disclosed. The mobile terminal receives a file cleaning instruction from a user. In response to the file cleaning instruction, the mobile terminal identifies cache files based on the cache files' associated information and past user activities on the cache files and groups the identified cache files and their associated information into multiple cache file categories. At least one of the multiple cache file categories is located in an extended storage device of the mobile terminal (e.g., a SD card). Next, the mobile terminal displays information of the multiple cache file categories on the display, each cache file category having an associated file cleaning option and cleans at least one of the multiple cache file categories from the mobile terminal in accordance with a user choice of the corresponding file cleaning option.

Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.

Abstract: Provided are a computer program product, system, and method for considering input/output workload and space usage at a plurality of logical devices to select one of the logical devices to use to store an object. A determination is made of a logical device to store the object based on workload scores for each of the logical devices indicating a level of read and write access of objects in the logical device and space usage of the logical devices. The object is written to the determined logical device.

Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.

Abstract: An information processing system includes: a shared memory including a plurality of regions comprising first region and second region; a memory token storing unit configured to store memory tokens, each of the memory tokens controlling access to a region of the shared memory; an access token storing unit configured to store access tokens for accessing a specific region of the shared memory, the access tokens including first access token to access the first region and second access token to access the second region; a processor configured to add the access tokens to a request for accessing the first region and transmit the request including the added access tokens; and a determination circuit configured to receive the transmitted request including the added access tokens, compare the added access tokens with a memory token corresponding to the first region, and control access to the first region based on the comparison.

Abstract: A data mirroring control apparatus includes a command distributing unit configured to transmit a first write command to a plurality of mirroring storage devices, the first write command including an instruction for data requested by a host to be written; and a memory lock setting unit configured to set a memory lock on the data requested by the host to be written among data stored in a host memory and configured to release the memory lock on the data after the data with the memory lock is written to the plurality of mirroring storage devices.

Abstract: A file storage method includes: splitting each of multiple files into one or more file block objects with different sizes; and writing the file block objects obtained from file splitting into corresponding large object storage files, wherein a preset number of large object storage files are pre-created in a storage apparatus, and storage spaces occupied by the preset number of large object storage files in the storage apparatus are continuous.

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Abstract: A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.

Abstract: In general, the technology relates to a method and system for writing data to persistent storage. More specifically, embodiments of the technology relate to writing data to vaulted memory segments in persistent storage using pre-defined multicast address groups. Further, embodiments of the technology take into account the current state of the persistent storage in order to select the vaulted memory segments in which to store the data.

Abstract: In a decode stage of hardware processor pipeline, one particular instruction of a plurality of instructions is decoded. It is determined that the particular instruction requires a memory access. Responsive to such determination, it is predicted whether the memory access will result in a cache miss. The predicting in turn includes accessing one of a plurality of entries in a pattern history table stored as a hardware table in the decode stage. The accessing is based, at least in part, upon at least a most recent entry in a global history buffer. The pattern history table stores a plurality of predictions. The global history buffer stores actual results of previous memory accesses as one of cache hits and cache misses.

Abstract: A data mirroring control apparatus includes a command distributing unit configured to transmit a first write command to a plurality of mirroring storage devices, the first write command including an instruction for data requested by a host to be written; and a memory lock setting unit configured to set a memory lock on the data requested by the host to be written among data stored in a host memory and configured to release the memory lock on the data after the data with the memory lock is written to the plurality of mirroring storage devices.

Abstract: In one general embodiment, a tape drive system includes: a read channel; a write channel; logic configured to receiving a request for a write operation to be performed in a tape drive; logic configured to determine an optimum a write procedure in response to receiving the request, the determining being based on expected writing times of each of a plurality of write procedures and an expected transaction size of a next write operation; and logic configured to invoke the determined optimum write procedure in response to determining the optimum write procedure.

Abstract: Systems, methods and or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.

Abstract: A computer program product includes a computer readable storage medium having program instructions executable by a tape drive to cause the tape drive to perform a method comprising: receiving, at the tape drive, a request for a write operation to be performed in the tape drive; determining, by the tape drive, an expected transaction size of a next write operation; comparing, by the tape drive, the expected transaction size of the next write operation to each of a first transaction size threshold and a second transaction size threshold in response to receiving the request; determining, by the tape drive, an optimum a write procedure based at least in part on the comparison; and invoking, by the tape drive, the optimum write procedure in response to determining the optimum write procedure.

Abstract: A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.