Abstract: Partially overwriting a compression group without decompressing compressed data can consumption of resources for the decompression. A storage server partially overwrites the compression group when a file block identifier of a client's write request resolves to the compression group. The compression group remains compressed while the partial overwriting is performed.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.

Abstract: Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.

Abstract: In one general embodiment, a method includes receiving a request for a write operation to be performed in a tape drive; determining a capacity margin ratio of the tape drive; determining an optimum a write procedure based at least in part on the capacity margin ratio; and invoking the optimum write procedure in response to determining the optimum write procedure. The optimum write procedure is selected from the group consisting of: a backhitch write procedure, a same wrap backhitchless flush (SWBF) write procedure, and a recursively accumulating backhitchless flush (RABF) write procedure. Systems and computer program products configured to perform similar techniques are also disclosed.

Abstract: A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The computer system further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue.

Abstract: A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The method further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue. The method further comprises, a cache traffic monitor of the central processing unit, transmitting the input-output data in an implicit input-output transmittal range between the cache traffic monitor and the aggregation queue, wherein the cache traffic monitor transmits cache protocol of the central processing unit to the memory management unit.

Abstract: A programmable logic controller (PLC) with changing memory access times is intended to interact with a subordinate system, i.e., a discontinuous virtualized system, wherein a computation apparatus is provided, in which the PLC is implemented and in which the system that is subordinate to the PLC with respect to an operation to access the memory access is implemented. A memory to which a component of the PLC has access is integrated in the PLC. Also implemented in the computation apparatus is a proxy device that coordinates access to the memory of the PLC by the subordinate system such that simultaneous access by the component of the PLC has priority over access by the subordinate system and it is thus possible to ensure that the PLC always complies with a predefined cycle time of the PLC.

Abstract: A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.

Abstract: The interface for inter-thread communication between a plurality of threads including a number of producer threads for producing data objects and a number of consumer threads for consuming the produced data objects includes a specifier and a provider. The specifier is configured to specify a certain relationship between a certain producer thread of the number of producer threads which is adapted to produce a certain data object and a consumer thread of the number of consumer threads which is adapted to consume the produced certain data object. Further, the provider is configured to provide direct cache line injection of a cache line of the produced certain data object to a cache allocated to the certain consumer thread related to the certain producer thread by the specified certain relationship.

Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.

Abstract: In a first embodiment, a method and computer program product for use in a storage system comprising quiescing IO commands the sites of an ACTIVE/ACTIVE storage system, the active/active storage system having at least two storage sites communicatively coupled via a virtualization layer, creating a change set, unquiescing IO commands by the virtualization layers, transferring data of a change set to the other sites of the active/active storage system by the virtualization layer, and flushing the data by the virtualization layer. In a second embodiment, a method and computer program product for use in a storage system comprising fracturing a cluster of an active/active storage system; wherein the cluster includes at least two sites, stopping IO on a first site of the cluster; and rolling to a point in time on the first site.

Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

Abstract: Technologies are described for implementing a default migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. Default migration behavior can be overridden by user-specified values for tier age residency policy, demotion policy, tier occupancy of volumes, and tier assignment. Data migration can be paused by the user and resumed by the user.

Abstract: According to the prior art, when requesters having different I/O access processing abilities compete when accessing a target, latency is extended via accesses from a requester having a lower I/O access performance, according to which the number of I/Os issued per unit time (data processing quantity) cannot be increased, and the processing performance of the system cannot be improved. According to the present invention, when requesters compete in accessing a target, the request having a lower requester performance (having a longer processing time per single I/O) is processed (started) in a prioritized manner. Thereby, the number of I/O processes per unit time can be increased, and the processing performance of the whole storage system can be improved.

Abstract: A method and system for reducing memory power usage are disclosed. The method and system comprise receiving at least one low-priority command and delaying execution of the at least one low-priority command until a predetermined event occurs, wherein the memory remains in a low-power mode until the predetermined event occurs.

Abstract: In a virtual machine, swap activities of a hypervisor and a guest OS are reconciled so that redundant input-output operations (IOs) can be avoided and a synchronous response time of the virtual machine improved. This is achieved with a map of memory pages to blocks of storage. For a write IO to write contents of a memory page into a target block, the map is examined to see if it contains a valid entry for the memory page. If the map contains the valid entry, the write IO is prevented from being issued and a data structure is updated so that subsequent IOs to the target block is redirected from the target block to a block that is associated with the physical memory page in the valid entry. On the other hand, if the map does not contain the valid entry, the write IO is issued.

Abstract: Technologies are described for implementing a default migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. Default migration behavior can be overridden by user-specified values for tier age residency policy, demotion policy, tier occupancy of volumes, and tier assignment. Data migration can be paused by the user and resumed by the user.

Abstract: A data storage device includes a non-volatile memory device including a memory cell array, where the memory cell array includes a first region and a second region, and a memory controller configured to judge whether a size of data externally provided according to a write request exceeds a reference size, and to control the non-volatile memory device according to a judgment result. When the externally provided data exceeds the reference size, the memory controller controls the non-volatile memory device such that a portion of the externally provided data is stored in the second region via a main program operation and such that a remainder of the externally provided data is stored in the first region via a buffer program operation.