Patents Examined by Caridad Everhart
  • Patent number: 10355243
    Abstract: A display apparatus includes a substrate, a display arranged on the substrate and including a plurality of display elements, and an encapsulator arranged on the display and encapsulating the display. The encapsulator may include at least one inorganic film and at least one organic film, and the at least one organic film may include a matrix and an ultraviolet light absorbent dispersed in the matrix.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonmin Yun, Yisu Kim, Eungseok Park, Byoungduk Lee, Yoonhyeung Cho, Yongchan Ju
  • Patent number: 10354941
    Abstract: A heat sink capable of dissipating heat concentrating on a chip portion of a power semiconductor device module efficiently is provided. A heat sink (20) includes a heat sink body (21) in which a power semiconductor device module (10) having a plurality of power semiconductor devices (11) is placed on a cooling surface F1 and which radiates heat generated by the power semiconductor device (11); and a heat dissipation structure portion (25) having a higher heat conductivity than the heat sink body (21) and capable of dissipating heat generated by the power semiconductor device (11), wherein the heat dissipation structure portion (25) is provided at a position overlapping the power semiconductor device (11) disposed in the power semiconductor device module (10) in a direction (Z) orthogonal to the cooling surface (F1) of the heat sink body (21).
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 16, 2019
    Assignee: FANUC CORPORATION
    Inventors: Masato Watanabe, Taku Sasaki
  • Patent number: 10347856
    Abstract: The present disclosure relates to a light detector. The light detector includes a first electrode, a second electrode, a current detector, a power source and a nano-heterostructure. The nano-heterostructure is electrically coupled with the first electrode and the second electrode. The nano-heterostructure includes a first carbon nanotube, a second carbon nanotube and a semiconductor layer. The semiconductor layer includes a first surface and a second surface opposite to the first surface. The first carbon nanotube is located on the first surface, the second carbon nanotube is located on the second surface.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: July 9, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10347860
    Abstract: A display device includes a substrate including a display area and a non-display area. The display device further includes a plurality of pixels in the display area of the substrate. The display device additionally includes a plurality of gate lines and a plurality of data lines respectively connected to the plurality of pixels. The display device further includes a plurality of insulative step portions disposed in the non-display area of the substrate and arranged in a first direction parallel to sides of the display area. The display device further includes a crack detection line in the non-display area and extending primarily in the first direction. The crack detection line includes a first portion which does not overlap the plurality of insulative step portions, and a second portion overlapping each of the insulative step portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Keun Soo Lee, Neung Ho Cho
  • Patent number: 10347742
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton Villiers
  • Patent number: 10347487
    Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Che-Chi Lee, Hiromitsu Oshima
  • Patent number: 10347682
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Sionyx, LLC
    Inventors: Homayoon Haddad, Jutao Jiang
  • Patent number: 10347310
    Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data includes a fixed layer, a barrier layer, and a composite free layer. A barrier layer is disposed between a fixed layer and a composite free layer. A composite free layer includes an in-plane anisotropy free layer, a perpendicular magnetic anisotropy (PMA) inducing layer, and a ferromagnetic amorphous layer. A PMA-inducing layer may be disposed such that an in-plane anisotropy free layer is between a barrier layer and the PMA-inducing layer. A ferromagnetic amorphous layer may be disposed between an in-plane anisotropy free layer and a PMA-inducing layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Young-Suk Choi
  • Patent number: 10347483
    Abstract: Structure or device comprising a hexagonal crystal layer or hexagonal crystal substrate, and a (001)-oriented rare earth nitride epitaxial layer on the hexagonal crystal layer or hexagonal crystal substrate.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 9, 2019
    Inventors: Franck Natali, Stéphane Ange Vézian, Jay Ross Peng Cheong Chan, Benjamin John Ruck, Harry Joseph Trodahl
  • Patent number: 10340325
    Abstract: A flexible display is disclosed. In one aspect, the flexible display includes a substrate and a plurality of first display layers formed on an upper surface of the substrate. The substrate includes a plurality of upper grooves, each of which defines a first opening in the upper surface and a plurality of lower grooves, each of which defines a second opening in a lower surface of the substrate. The upper grooves and the lower grooves are alternately arranged.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Un Byoll Ko, Byeong Hwa Choi
  • Patent number: 10340428
    Abstract: There is provided an electro-optical device including a light-emitting layer that has a first light-emitting element and a second light-emitting element which are adjacent to each other and a color filter layer that has a first color filter provided corresponding to the first light-emitting element and a second color filter provided corresponding to the second light-emitting element, in which an inter-element distance between the first light-emitting element and the second light-emitting element is 1.5 ?m or less, and a thickness of layer between the light-emitting layer and the color filter layer is 6 times or less the inter-element distance.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takeshi Koshihara
  • Patent number: 10340364
    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Tenko Yamashita, Xin Miao, Wenyu Xu
  • Patent number: 10332980
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 25, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Zhaoxu Shen
  • Patent number: 10332880
    Abstract: Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET (Fin Field Effect Transistor) devices. For example, a semiconductor device includes a FinFET device and a vertical fin resistor device formed on a semiconductor substrate. The FinFET device includes a vertical semiconductor fin which includes a structural profile that is defined by dimensions of width W, height H, and length L. The vertical fin resistor device includes a vertical fin structure which is formed of a resistive material (e.g., polysilicon or amorphous silicon), and which has a structural profile that is defined by dimension of width W1, height H1, and length L1. The structural profiles of the vertical semiconductor fin of the FinFET device and the vertical fin structure of the vertical fin resistor device have at least one corresponding dimension that is substantially the same.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu
  • Patent number: 10332927
    Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: June 25, 2019
    Assignee: Sony Corporation
    Inventor: Masaki Haneda
  • Patent number: 10325897
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Patent number: 10325803
    Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Kuenle, Gerhard Schmidt, Martin Sporn, Markus Kahn, Juergen Steinbrenner, Ravi Joshi
  • Patent number: 10325861
    Abstract: Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventor: Giuseppe Miccoli
  • Patent number: 10319750
    Abstract: A display device includes a substrate, an insulating layer, and a crack-sensing line. The substrate includes a display area having a plurality of pixels to display images, and a non-display area surrounding the display area. The insulating layer is disposed in the non-display area and includes a recess. The crack-sensing line is disposed in and extends along the recess, and electrically connected to at least one of the pixels. The recess is disposed at a surface or inside of the insulating layer, and extends along the non-display area.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Display Co., Ltd
    Inventors: Sun Park, Ji Won Sohn, Su Yeon Yun
  • Patent number: 10319686
    Abstract: A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ignazio Bruno Mirabella