Patents Examined by Caridad Everhart
  • Patent number: 11114389
    Abstract: A substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area. The upper side rail includes an upper stress relief structure and an upper reinforcing structure. The upper stress relief structure surrounds the upper chip attach area. The upper reinforcing structure surrounds the upper stress relief structure. A stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure. A structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 7, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shun Sing Liao
  • Patent number: 11114500
    Abstract: A display device includes a substrate including a display area having a plurality of pixel areas and a non-display area located around the display area; a circuit element layer including a circuit element in each of the pixel areas and a reference voltage wiring in the non-display area, the reference voltage wiring being electrically coupled to the circuit element; and a display element layer including a first pixel electrode on the circuit element layer in each of the pixel areas, a second pixel electrode located opposite to the first pixel electrode, a plurality of light emitting elements between the first pixel electrode and the second pixel electrode, and a first wiring on the circuit element layer in the non-display area, wherein the first wiring is directly coupled to the reference voltage wiring in the non-display area.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Jun Lee, Hyo Chul Lee
  • Patent number: 11114341
    Abstract: A laser processing method for a substrate with a device formed on a front surface thereof and including an electrode pad, the method including: a laser beam applying step of applying the laser beam to the back surface of the substrate to form a fine hole in the substrate at a position corresponding to the electrode pad; a detecting step of detecting first plasma light emitted from the substrate at the same time that the fine hole is formed in the substrate by the laser beam applied thereto, and second plasma light emitted from the electrode pad; and a laser beam irradiation finishing step of stopping application of the laser beam when the second plasma light is detected in the detecting step. A peak power density of the laser beam to be applied is set in a range from 175 GW/cm2 or less to 100 GW/cm2 or more.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 7, 2021
    Assignee: DISCO CORPORATION
    Inventor: Hiroshi Morikazu
  • Patent number: 11114630
    Abstract: A display panel is provided, including a substrate on a base, a transistor stack on the substrate, and a fluorescent layer between the base and the transistor stack. The fluorescent layer is configured to prevent light from damaging an active layer in the transistor stack in a laser lift-off process, and an orthographic projection of the fluorescent layer on the base overlaps an orthographic projection of the active layer on the base. A display device comprising the display panel, and a manufacturing method of the display panel are further provided.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Shipei Li, Qi Yao, Wusheng Li, Jiangnan Lu, Huili Wu, Fang He, Renquan Gu, Dongsheng Yin, Sheng Xu, Wei He
  • Patent number: 11107893
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Patent number: 11104695
    Abstract: Metal halide perovskite crystals, composite materials that include metal halide perovskite crystals and a polymeric matrix material, devices that include metal halide perovskite crystals, and methods of forming metal halide perovskite crystals, composite materials, and devices. The devices may include optoelectronic devices, such as light-emitting diodes. The light-emitting diodes may emit red light.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 31, 2021
    Assignee: The Florida State University Research Foundation, Inc.
    Inventors: Biwu Ma, Yu Tian
  • Patent number: 11101282
    Abstract: According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyasu Sato
  • Patent number: 11094854
    Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 17, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Hirofumi Ichikawa, Masaki Hayashi, Shimpei Sasaoka, Tomohide Miki
  • Patent number: 11093824
    Abstract: The present disclosure provides a neuromorphic device and a method of driving the same. The neuromorphic device of the present disclosure includes a channel, the magnetization direction of which is changed as a plurality of data is integrated, first and second magnetization regulators formed on both ends of the channel and responsible for changing the magnetization direction of the channel according to a plurality of input data, and a controller formed on the channel between the first and second magnetization regulators and responsible for firing data equal to or greater than a critical value integrated in the channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 17, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 11087971
    Abstract: The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Lung Lin, Hau-Yi Hsiao, Chih-Hui Huang, Kuo-Hwa Tzeng, Cheng-Hsien Chou
  • Patent number: 11088054
    Abstract: A lead frame includes a die pad having a pad top surface and a pad bottom surface opposite to the top pad surface, a plurality of leads, each having a top lead surface and a bottom lead surface opposite to the top lead surface and disposed around the die pad, and a first molding compound disposed between the die pad and each of the leads. The first molding compound exposes the top pad surface of the die pad by covering a portion of the periphery of the top pad surface of the die pad. A method for manufacturing the lead frame is also disclosed.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ying-Chung Chen, Hui-Chung Liu
  • Patent number: 11084713
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Patent number: 11084127
    Abstract: A laser lift-off method is disclosed. The laser lift-off method includes: controlling a laser beam to penetrate a substrate along a first irradiation direction, so as to scan an interface between a material layer and the substrate stacked on each other, wherein there is at least one particle on a side of the substrate away from the material layer, and a region of the interface not irradiated by the laser beam along the first irradiation direction is an occluded region; controlling another laser beam to penetrate the substrate along a second irradiation direction, so as to scan the interface between the material layer and the substrate, so that at least a part of the occluded region is irradiated by the another laser beam along the second irradiation direction; and separating the material layer from the substrate.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 10, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ting Wang, Zhiliang Jiang, Zhenli Zhou
  • Patent number: 11075252
    Abstract: A foldable display device includes: a first substrate, a first thin-film transistor layer on the first substrate, a light emitting element layer on the first thin-film transistor layer, and a fingerprint sensor layer to receive light reflected by an external object. The fingerprint sensor layer includes: a second substrate under the first substrate, a second thin-film transistor layer under the second substrate, and a light receiving element layer under the second thin-film transistor layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Go Eun Cha, Keum Dong Jung, Suk Kim, Soo Jung Lee
  • Patent number: 11069737
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 20, 2021
    Assignee: SiOnyx, LLC
    Inventors: Homayoon Haddad, Jutao Jiang
  • Patent number: 11069813
    Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
  • Patent number: 11062948
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: July 13, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11063008
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11056487
    Abstract: Certain aspects of the present disclosure generally relate to a single diffusion break having a conductive portion. An example semiconductor device generally includes a first semiconductor region, a second semiconductor region, a dielectric region, and a single diffusion break (SDB). The dielectric region is disposed between the first semiconductor region and the second semiconductor region. The SDB intersects at least one of the first semiconductor region or the second semiconductor region, and the SDB comprises an electrically conductive portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 11056502
    Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Cheon Baek