Patents Examined by Caridad Everhart
  • Patent number: 10790001
    Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Nathan Philip Marchack
  • Patent number: 10784236
    Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Kapil V. Sakariya, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 10784410
    Abstract: Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and/or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and/or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 22, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Tien Khee Ng, Chao Zhao, Davide Priante, Boon S. Ooi, Mohamed Ebaid Abdrabou Hussein
  • Patent number: 10777551
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 10777503
    Abstract: A method for contacting a metallic contact pad embedded in a printed circuit board layer sequence, comprising the steps of producing a first hole matrix having a plurality of holes in a surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, of applying a metal layer in order to at least partly fill the holes of the first hole matrix, of producing a second hole matrix having a plurality of holes in the surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, wherein the holes of the second hole matrix are arranged in a manner offset relative to the holes of the first hole matrix, and of applying a metal layer in order to at least partly fill the holes of the second hole matrix, and a correspondingly produced printed circuit board.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 15, 2020
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle
  • Patent number: 10777677
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10777569
    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuto Omizu, Takashi Hashimoto, Hideaki Yamakoshi
  • Patent number: 10770563
    Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 10770554
    Abstract: There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually increased from a substrate side toward a surface side of the drift layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 8, 2020
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Yoshinobu Narita
  • Patent number: 10770447
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Patent number: 10756960
    Abstract: A light-emitting device comprises a first light-emitting semiconductor stack comprising a first active layer; a second light-emitting semiconductor stack below the first light-emitting semiconductor stack, wherein the second light-emitting semiconductor stack comprises a second active layer; a reflector between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack; a protecting layer between the reflector and the second light-emitting semiconductor stack; and wherein the first light-emitting semiconductor stack further comprises a first semiconductor layer and a second semiconductor layer sandwiching the first active layer, the second light-emitting semiconductor stack further comprises a third semiconductor layer and a fourth semiconductor layer sandwiching the second active layer, wherein the second semiconductor layer has a first band gap, the third semiconductor layer has a second band gap, and the protecting layer has a third band gap between the first band gap an
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 25, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Chiang Lu, Yi-Chieh Lin, Wen-Luh Liao, Shou-Lung Chen, Chien-Fu Huang
  • Patent number: 10756298
    Abstract: An OLED device comprising a substrate with a top surface; a first electrode covering the top surface of the substrate; a first insulating structure patterned over a portion of the first electrode where the pattern defines an inside area of the first electrode that is completely surrounded by the insulating structure, and an outside area of the first electrode not covered by the insulating structure; at least one organic layer for light emission within the inside area defined by the insulating structure; a second electrode over the at least one organic layer within the inside area defined by the insulating structure and at least partially over the first insulating structure; a cover slip located at least over the second electrode in the inside area defined by the insulating structure; and an electrically conductive solder seal making a hermetic seal between the insulating structure and the cover slip where the solder seal is in electrical contact with the second electrode.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 25, 2020
    Inventors: John Hamer, Scott Stickel, Timothy Floyd Spencer
  • Patent number: 10756002
    Abstract: A packaged device, having a package, including a first dissipative region, a second dissipative region, a first connection element and a second connection element. A die of semiconductor material is arranged within the package, carried by the first dissipative region. The first and second dissipative regions extend at a distance from each other, and the first and second connection elements extend at a distance from each other between the first and second dissipative regions. The first dissipative region, the second dissipative region, the first connection element, and the second connection element are hollow and form a circuit containing a cooling liquid.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristiano Gianluca Stella, Francesco Salamone
  • Patent number: 10755607
    Abstract: A display device includes a display panel having a first region, a second region spaced apart from the first region, and a bending region between the first region and the second region, the bending region being bent along a bending axis, a protective film including a first part on a first surface of the first region of the display panel, the first part having an opening at a center thereof that exposes the first surface of the display panel, and a second part on a first surface of the second region of the display panel, and a functional layer on the first surface of the display panel exposed by the opening.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minsang Kim, Seungwook Kwon, Ohjune Kwon, Hyojeong Kwon, Doohwan Kim
  • Patent number: 10749135
    Abstract: Provided is an electrode structure having a transparent electrode, a light blocking pattern provided on the transparent electrode, an auxiliary electrode pattern provided on the light blocking pattern, and an organic insulating pattern covering the light blocking pattern and the auxiliary electrode pattern, wherein a line width of the light blocking pattern is larger than a line width of the auxiliary electrode pattern. Also provided are an electronic device including the electrode structure, and a method of manufacturing the electrode structure.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 18, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Yong Goo Son, Song Ho Jang, Jiehyun Seong, Kiseok Lee, Seung Heon Lee
  • Patent number: 10741710
    Abstract: Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes may include a photon-reflective material.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hans-Juergen Eickelmann, Ruediger Kellmann, Hartmut Kuehl, Markus Schmidt
  • Patent number: 10741789
    Abstract: A flexible display device includes a flexible display panel having a bending area to be folded, and including a display substrate, and a thin-film encapsulation layer above the display substrate, a driving portion, and a function layer below the flexible display panel, and including a step portion below which the flexible display panel is electrically connected to the driving portion.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soohee Oh, Hyunggyu Park, Seonggeun Won, Hirotsugu Kishimoto
  • Patent number: 10741750
    Abstract: The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor substrate, a first pillar and a second pillar over the semiconductor substrate, an isolation layer over the semiconductor substrate, and a first contact pad and a second contact pad embedded in the isolation layer. A first upper surface of the first pillar is higher than a second upper surface of the second pillar. The first pillar and the second pillar are laterally surrounded by the isolation layer. The first contact pad is disposed over the first pillar. The second contact pad is disposed over the second pillar, and a first pad width of the first contact pad is not greater than a second pad width of the second contact pad.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 11, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jar-Ming Ho
  • Patent number: 10741394
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 11, 2020
    Assignees: ASM IP HOLDING B.V., IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN
    Inventors: Jan Willem Maes, Werner Knaepen, Roel Gronheid, Arjun Singh
  • Patent number: 10734304
    Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone