Patents Examined by Caridad Everhart
  • Variable frequency drive operation to avoid overheating
    Patent number: 10314200
    Abstract: Operation of a variable frequency in a manner configured to avoid overheating is provided. In one form, a method includes providing a variable frequency drive that includes a switching device in thermal communication with a heat sink including a thermal mass. The method further includes operating the drive in a first mode before active cooling of the heat sink is established and a second mode following the first mode. Operation of the drive in the first mode includes operating the switching device in a first switching frequency mode, and the first switching frequency mode and the thermal mass of the heat sink are selected to provide a temperature of the switching device below a predetermined threshold before active cooling of the heat sink is established. Further embodiments, forms, features, and aspects shall become apparent from the description and drawings.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 4, 2019
    Assignee: Trane International Inc.
    Inventors: Benjamin James Sykora, Nathan Thomas West, David Marshall Foye, Korwin Jay Anderson
  • Wide-band high speed communications channel for cryogenic applications
    Patent number: 10305193
    Abstract: A high speed radio frequency signal interconnect device provides for signal communication within a system at cryogenic temperatures. The device includes a plurality of conductive traces provided on a first dielectric substrate where the ends of the traces have a predetermined shape. A second dielectric substrate covers the first dielectric substrate leaving the ends of the traces exposed. A connector is coupled to each respective end and includes pins coupled to a respective trace. Each connector is configured to define a respective isolating chamber about each of the first ends of the conductive traces where the pins are attached.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 28, 2019
    Assignee: Raytheon Company
    Inventors: Amedeo Larussi, David A. Buell, Craig R. Adams, Christopher Moshenrose
  • System for integrating preceding steps and subsequent steps
    Patent number: 10304675
    Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 28, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Michihiro Inoue, Shiro Hara, Fumito Imura, Arami Saruwatari, Sommawan Khumpuang
  • Semiconductor device and manufacturing method thereof
    Patent number: 10304962
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Fabrication and use of large-grain templates for epitaxial deposition of semiconductor materials
    Patent number: 10304989
    Abstract: Methods for growing and using large-grain templates are provided. According to an aspect of the invention, a method includes depositing a small-grain layer of a semiconductor material; treating the small-grain layer such that the small-grain layer becomes a large-grain layer; and growing an epitaxial layer of the semiconductor material on the large-grain layer. A ratio of an average grain size of the small-grain layer to a thickness of the small-grain layer is less than 1.0, and a ratio of an average grain size of the large-grain layer to a thickness of the large-grain layer is greater than 1.5.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 28, 2019
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: David Scott Albin, Wyatt Keith Metzger, James Michael Burst, Eric Michael Colegrove, Joel Nathan Duenow
  • Semiconductor device
    Patent number: 10297516
    Abstract: A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface. An outer packaging resin covers the semiconductor element and the base, and is fixed to the base by filling the groove. A bottom of the groove includes a first recess-projection having a first amplitude and a first repetition interval along an extending direction of the groove. The first recess-projection includes a second recess-projection having a second amplitude smaller than the first amplitude and a second repetition interval shorter than the first repetition interval along the extending direction of the groove.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masayuki Nagamatsu, Shinya Marumo, Junichi Kimura, Tatsuya Kunisato, Ryosuke Usui
  • LED bracket, LED device and LED display screen
    Patent number: 10290783
    Abstract: An LED bracket, an LED device and an LED display screen are disclosed. The LED bracket includes a metal bracket and a cup cover wrapping the metal bracket. The metal bracket includes a first metal pin embedded into the cup cover and a second metal pin exposed from the cup cover. A part, located on a top of the second metal pin, in the cup cover is a reflection cup. A light absorbing layer is disposed on a part of an outer side face of the reflection cup.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Foshan NationStar Optoelectronics Co., Ltd.
    Inventors: Chuanbiao Liu, Xiaofeng Liu, Zongxian Xie, Qiang Zhao, Kailiang Fan, Kuai Qin, Lu Yang
  • Semiconductor device and manufacturing method of the same
    Patent number: 10290609
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Ying-Ching Shih, Pu Wang, Chen-Hua Yu
  • Array of hole-type surround gate vertical field effect transistors and method of making thereof
    Patent number: 10290681
    Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chao Feng Yeh, Jongsun Sel, Zhen Chen
  • Semiconductor device
    Patent number: 10290711
    Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: May 14, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Image sensor device and method of forming same
    Patent number: 10290671
    Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Solid-state imaging element and imaging device
    Patent number: 10283544
    Abstract: To improve detection efficiency in a solid-state imaging element including a SPAD in which an electrode and wiring are placed in a central portion. A solid-state imaging element includes a photodiode and a light collecting section. The photodiode includes a light receiving surface and an electrode placed on the light receiving surface, and that outputs an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode. The light collecting section causes light from a subject to be collected in the light receiving surface other than a region where the electrode is placed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 7, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuhi Yorikado, Atsushi Toda, Susumu Inoue
  • Display device and method for manufacturing the same
    Patent number: 10283570
    Abstract: A display device includes a substrate having a red pixel region, a blue pixel region, and a green pixel region. An anode is on the substrate, a light-emitting layer is on the anode, and a cathode is on the light-emitting layer, wherein the light-emitting layer includes a red light-emitting layer emitting red light on the red pixel region, a blue light-emitting layer emitting blue light on the blue pixel region, and a green light-emitting layer emitting green light on the red pixel region, the blue pixel region, and the green pixel region. Each of the red light, the blue light, and the green light is resonated between the anode and the cathode.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 7, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangwoo Pyo, Hajin Song, Jihwan Yoon, Heunseung Lee
  • Stacked image sensor having a barrier layer
    Patent number: 10283547
    Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting Chen, Shu-Ting Tsai, Cheng-Ying Ho, Tzu-Hsuan Hsu, Shih Pei Chou
  • Method for manufacturing flexible electrical device
    Patent number: 10280339
    Abstract: A method for manufacturing a flexible electrical device is provided and includes the following steps. A carrier substrate is provided. A releasing layer is formed on the carrier substrate. A flexible substrate is formed on the releasing layer. The flexible substrate has a first surface facing the releasing layer and a second surface opposite to the first surface. The flexible substrate is not in contact with the carrier substrate. A device layer is formed on the flexible substrate. The device layer has a third surface facing the flexible substrate and a fourth surface opposite to the third surface. The flexible substrate is separated from the releasing layer, and the releasing layer remains on the carrier substrate. Accordingly, the releasing layer and the carrier substrate can be recycled for forming another flexible electrical device.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: May 7, 2019
    Assignees: HannStar Display (Nanjing) Corporation, HannStar Display Corporation
    Inventors: Yen-Chung Chen, Chen-Hao Su
  • Polarization electric field assisted hole supplier and p-type contact structure, light emitting device and photodetector using the same
    Patent number: 10276746
    Abstract: A hole supplier and p-contact structure for a light emitting device or a photodetector includes a p-type group III nitride structure and a hole supplier and p-contact layer made of Al-containing group III nitride formed on the p-type group III nitride structure and being under a biaxial in-plane tensile strain, the hole supplier and p-contact layer has a thickness in the range of 0.6-10 nm, and the p-type group III nitride structure is formed over an active region of the light emitting device or photodetector. A light emitting device and a photodetector with a hole supplier and p-contact structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 30, 2019
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Ying Gao, Ling Zhou
  • Stable organic photosensitive devices with exciton-blocking charge carrier filters utilizing high glass transition temperature materials
    Patent number: 10276817
    Abstract: Disclosed herein are stable organic photosensitive devices including at least one exciton-blocking charge carrier filter. The filters comprise a mixture of at least one wide energy gap material having a sufficiently high glass transition temperature, e.g., higher than the temperature or temperature range at which the device typically operates, higher than a highest operating temperature of the device, higher than a threshold temperature value, etc. and at least one electron or hole conducting material. As described herein, the novel filters simultaneously block excitons and conduct the desired charge carrier (electrons or holes).
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 30, 2019
    Assignees: University of Southern California, The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Quinn Burlingame, Xin Xiao, Kevin Bergemann, Anurag Panda, Jeramy D. Zimmerman, Brian E. Lassiter, Mark E. Thompson, Andrew N. Bartynski, Cong Trinh
  • Optoelectronic component
    Patent number: 10276762
    Abstract: An optoelectronic component includes a carrier, and a light source arranged on a surface of the carrier, said light source including at least one luminous surface formed by at least one light-emitting diode, wherein a transparent converter-free spacer is arranged on the luminous surface such that a distance is formed between the luminous surface and a spacer surface of the spacer facing away from the luminous surface, and wherein the light source is potted by a potting compound such that the spacer surface is formed extending flush with a potting compound surface facing away from the surface of the carrier and a surface formed by a spacer surface and the potting compound surface is plane.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: April 30, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: David Racz, Michael Zitzlsperger, Günter Spath
  • Method for manufacturing semiconductor device
    Patent number: 10276395
    Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee
  • Neuristor-based reservoir computing devices
    Patent number: 10275706
    Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 30, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Matthew D. Pickett