Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Abstract: A light scattering film includes a light transmissive base having a plurality of holes, wherein each of the plurality of holes has a diameter ranging from about 100 nm to about 5 ?m, and wherein a gap among adjacent ones of the plurality of holes is about two times to about five times of an average of the diameters of the plurality of holes.

Abstract: A method of processing a reconstituted wafer that supports IC chips includes operably disposing the reconstituted wafer in a lithography tool that has a depth of focus and a focus plane and that defines exposure fields on the reconstituted wafer, wherein each exposure field includes at least one of the IC chips. The method also includes scanning the reconstituted wafer with a line scanner to measure a surface topography of the reconstituted wafer as defined by the IC chips. The method also includes, for each exposure field: i) adjusting a position and/or an orientation of the reconstituted wafer so that a photoresist layers of the IC chips within the given exposure field fall within the depth of focus; and ii) performing an exposure with the lithography tool to pattern the photoresist layers of the IC chips in the given exposure field.

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

Abstract: An example film forming device is provided with: a chamber for forming a film on a substrate; a supply tube for supplying a cleaning gas to the chamber; and a plasma generating unit, which is provided to the supply tube, and which generates plasma from the cleaning gas. The film forming device is characterized by being provided with: a temperature control unit that controls the temperature of the supply tube to temperature equal to or higher than a predetermined temperature; and a supply unit which supplies, each time when a previously set time equal to or shorter than 36 hours elapses, the chamber with the plasma thus generated by the plasma generating unit.

Abstract: The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material, wherein a first doping region (5) is formed by means of ion implantation (S2) of a first dopant in a first surface (3a) of a semiconductor substrate (3), and a second doping region (7) is formed by means of ion implantation (S3) or thermal indiffusion of a second dopant in the second surface (3b) of the semiconductor substrate. After the doping of the second surface, a cap (9b) acting as an outdiffusion barrier for the second dopant is applied and an annealing step (S4) is subsequently carried out.

Abstract: A method for manufacturing a graphite layer on an interstitial carbide layer, includes depositing a metal layer formed by one or more metals on a carbide substrate, the metal layer being able to form an interstitial carbide, the metal layer at least partially covering the carbide substrate; performing a heat treatment during which a temperature higher than the dissociation temperature of the carbide of the carbide substrate is applied; wherein the heat allows a reaction between the metal layer and the carbide substrate to form the interstitial carbide layer as well as a first part of the graphite layer at the surface of the interstitial carbide layer, and, when the metal layer only partially covers the carbide substrate, a formation of a second part of the graphite layer at the surface of the carbide substrate which is not covered with the metal layer.

Abstract: A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.

Abstract: There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.

Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.

Abstract: A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing chamber. The method comprising orienting a supporting surface of a substrate support in a first orientation relative to an output surface of a showerhead, where the first orientation of the supporting surface relative to the output surface is not coplanar, and depositing a first layer of material on a substrate disposed on the supporting surface that is oriented in the first orientation.

Abstract: A method for making a surgical guide for bone harvesting identifying in a three-dimensional image of a bone one or more sensitive anatomic structures and a volume of bone suitable for being removed. The volume is delimited by a portion of an outer surface of the bone defining a perimeter and by a mantle extending from the perimeter inside of the bone. The method also includes designing the surgical guide which includes defining a guide surface including a work area delimited by guide walls. The method also includes angling at least one of the guide walls so that the guide wall includes a face that constitutes a geometrical extension of a portion of the mantle when the guide is rested on the outer surface of the bone such that the face includes at least one segment forming a predetermined angle with respect to the guide surface.

Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

Abstract: A semiconductor device according to an embodiment of the disclosure includes: a first substrate; a TFT element provided on the first substrate with a first interlayer insulating layer interposed therebetween, and including a semiconductor layer and a gate electrode that is provided on the semiconductor layer with a gate insulating layer interposed therebetween; and a second substrate disposed to face the first substrate. The gate electrode includes a first electroconductive film and a second electroconductive film that has a light-shielding property in order from side of the semiconductor layer. The second electroconductive film extends from a side face to a bottom face of each of a pair of openings that are provided to interpose the semiconductor layer.

Abstract: A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.

Abstract: A flexible display device includes a flexible display panel having a bending area to be folded, and including a display substrate, and a thin-film encapsulation layer above the display substrate, a driving portion, and a function layer below the flexible display panel, and including a step portion below which the flexible display panel is electrically connected to the driving portion.

Abstract: A light-emitting device comprises a first light-emitting semiconductor stack comprising a first active layer; a second light-emitting semiconductor stack below the first light-emitting semiconductor stack, wherein the second light-emitting semiconductor stack comprises a second active layer; a reflector between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack; a protecting layer between the reflector and the second light-emitting semiconductor stack; and wherein the first light-emitting semiconductor stack further comprises a first semiconductor layer and a second semiconductor layer sandwiching the first active layer, the second light-emitting semiconductor stack further comprises a third semiconductor layer and a fourth semiconductor layer sandwiching the second active layer, wherein the second semiconductor layer has a first band gap, the third semiconductor layer has a second band gap, and the protecting layer has a third band gap between the first band gap an