Patents Examined by Cassandra Cox
  • Patent number: 10277105
    Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die. Multi-output POL circuits may be used in conjunction with on-chip rail-selection and regulation circuitry to further improve efficiency.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 30, 2019
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Andrew T. D'Amico
  • Patent number: 10277219
    Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainald Sander, Andreas Meiser
  • Patent number: 10263432
    Abstract: A method for wireless power transmission is provided. The method comprising emitting, by a first antenna element of a transmitter, a first signal comprising a plurality of wireless power waves establishing a pocket of energy. The method further comprising emitting, by a second antenna element of the transmitter, a second signal different from the first signal. The second signal provides Wi-Fi access.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 16, 2019
    Assignee: Energous Corporation
    Inventors: Michael A. Leabman, Gregory Scott Brewer
  • Patent number: 10262956
    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: David Darmon, Avi Klein, Yehuda Salmon, Aharon Grabovsky, Ruben Attia
  • Patent number: 10256812
    Abstract: In accordance with an embodiment, a method of controlling a switch driver includes energizing a first inductor in a first direction with a first energy; transferring the first energy from the first inductor to a second inductor, wherein the second inductor is coupled between a second switch-driving terminal of the switch driver and a second internal node, and the second inductor is magnetically coupled to the first inductor; asserting a first turn-on signal at the second switch-driving terminal using the transferred first energy; energizing the first inductor in a second direction opposite the first direction with a second energy after asserting the first turn-on signal at the second switch-driving terminal; transferring the second energy from the first inductor to the second inductor; and asserting a first turn-off signal at the second switch-driving terminal using the transferred second energy.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 9, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Kennith Kin Leong, Wenduo Liu, Gerald Deboy
  • Patent number: 10250233
    Abstract: A semiconductor substrate includes a first portion and a second portion. The first portion of the substrate has a first deformation-stress sensor capable of supplying a first stress signal. The second portion of the substrate has a second deformation-stress sensor capable of supplying a second stress signal. The first stress signal and second stress signal are processed by a circuit to produce a compensation signal. The compensation signal is applied in feedback to one of the first and second stress signals to compensate for variations induced in said one of the first and second stress signals by stresses in the semiconductor substrate.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe Scilla
  • Patent number: 10250236
    Abstract: A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Sarma Vrudhula, Niranjan Kulkarni, Jinghua Yang
  • Patent number: 10250249
    Abstract: A circuit and method are provided for recuperating energy and decreasing driver power consumption in a switching converter. An inductor is directly connected between a gate driver and a gate electrode of a switch. A first burst pulse signal is generated, wherein energy from a power source is stored in the inductor and transferred to a parasitic capacitance of the switch. A driving pulse signal is subsequently generated to the gate electrode of the switch, wherein the gate voltage is equal to the supply voltage and no balancing current flows through the inductor. After the driving pulse signal is terminated a second burst pulse signal is generated, wherein energy is accumulated in the inductive element and returned to the power source. The energy provided from the power source during the first burst pulse signal is equal to the energy returned to the power source during the second burst pulse signal.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Bel Power Solutions Inc.
    Inventors: Ivan Feno, Raphael Bernhard, Michal Sir
  • Patent number: 10242749
    Abstract: Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 26, 2019
    Assignee: KANDOU LABS, S.A.
    Inventors: Armin Tajalli, Ali Hormati
  • Patent number: 10230360
    Abstract: The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christos Vezyrtzis, Pawel Owczarczyk
  • Patent number: 10230380
    Abstract: Phase-locked loop devices are provided where a correction factor is determined based on a correlation using a linear controller.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventor: Arash Pake Talei
  • Patent number: 10224906
    Abstract: A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Roh Yamamoto
  • Patent number: 10222817
    Abstract: A bandgap reference (BGR) circuit and method generates a constant voltage reference that is stable over temperature variations. The BGR circuit is composed of a proportional to absolute temperature (PTAT) stage, a complementary to absolute temperature (CTAT) stage, and an output stage interposed between the PTAT stage and the CTAT stage. The PTAT stage is configured to produce a PTAT current and the CTAT stage is configured to produce a CTAT current. The BGR circuit is configured to mirror the PTAT current and mirror the CTAT current to produce a mirrored PTAT current and a mirrored CTAT current in the output stage and the output stage is configured to combine the mirrored PTAT current and the mirrored CTAT current to generate the constant voltage reference.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 5, 2019
    Assignee: Cavium, LLC
    Inventor: JingDong Deng
  • Patent number: 10218337
    Abstract: A semiconductor device provides a plurality of circuit units arranged in parallel. Each of the plurality of circuit units includes a first signal line that transmits a first signal, which is an analog signal; a sending unit that sends a second signal; a receiving unit that receives the second signal; and a second signal line that transmits the second signal from the sending unit to the receiving unit. The distance between the first and second signal lines is shorter than the pitches at which the plurality of circuit units is arranged. The second signal is a pulse signal.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 26, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuharu Ota, Yasushi Matsuno, Takashi Muto, Daisuke Yoshida
  • Patent number: 10211994
    Abstract: A power sourcing equipment is provided. The power sourcing equipment is connected to an Ethernet cable. The power sourcing equipment includes a switching circuit, a power circuit, and a detection circuit. The power circuit is coupled to a power supply output terminal via the switching circuit. The detection circuit is configured to control a state of the switching circuit according to a first resistance between a first pin and a second pin of the Ethernet cable.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 19, 2019
    Assignee: SERCOMM CORPORATION
    Inventors: Chun-En Lin, Kuo-Fu Weng, Meng-Chien Chiang
  • Patent number: 10211826
    Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Terenzi, Davide Ugo Ghisu
  • Patent number: 10209723
    Abstract: A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 19, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yu-Hsiang Huang, Jyun-Yang Shih, Chun-Chia Chen
  • Patent number: 10209735
    Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock, the apparatus includes a first data latch and a second data latch configured in a ring topology with a negative feedback based on inter-connection through a four-phase level-shifted clock, the first data latch configured to receive a fourth phase and a second phase of the level-shifted clock and output a first phase and a third phase of the output clock along with a first phase and a third phase of the level-shifted clock in accordance with a first phase of the input clock, the second data latch configured to receive the first phase and the third phase of the level-shifted clock and output a second phase and a fourth phase of the output clock along with the second phase and the fourth phase of the level-shifted clock in accordance with a second phase of the input clock.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10205443
    Abstract: A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: February 12, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Fangjie Yang, Chuan-Ping Tu
  • Patent number: 10205387
    Abstract: A charge pump circuit includes N boosting circuits, (N?2) switching circuits and a control circuit. A kth boosting circuit includes a unidirectional component and a capacitor. A positive terminal of the unidirectional component of the kth boosting circuit is electrically connected to a negative terminal of a unidirectional component of a (k?1)th boosting circuit. A first terminal of the capacitor of the kth boosting circuit is electrically connected to a negative terminal of the unidirectional component of the kth boosting circuit. A (2i?1)th switching circuit selectively conducts a current path from a (2i?1)th boosting circuit to a first clock terminal or to a ground terminal according to a control signal of the control circuit. A (2i)th switching circuit selectively conducts a current path from a (2i)th boosting circuit to a second clock terminal or to the ground terminal according to the control signal of the control circuit.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 12, 2019
    Assignee: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Wen-Chi Lin, Cheng-Ta Wu, Keng-Nan Chen