Abstract: A charge pump circuit includes N boosting circuits, (N?2) switching circuits and a control circuit. A kth boosting circuit includes a unidirectional component and a capacitor. A positive terminal of the unidirectional component of the kth boosting circuit is electrically connected to a negative terminal of a unidirectional component of a (k?1)th boosting circuit. A first terminal of the capacitor of the kth boosting circuit is electrically connected to a negative terminal of the unidirectional component of the kth boosting circuit. A (2i?1)th switching circuit selectively conducts a current path from a (2i?1)th boosting circuit to a first clock terminal or to a ground terminal according to a control signal of the control circuit. A (2i)th switching circuit selectively conducts a current path from a (2i)th boosting circuit to a second clock terminal or to the ground terminal according to the control signal of the control circuit.

Abstract: A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N1/R1+

Abstract: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node.

Abstract: An exemplary embodiment of the disclosure provides a random data generation circuit which includes a phase difference detection circuit and a random data output circuit. The phase difference detection circuit detects a phase difference between a first clock signal and a second clock signal and outputs phase difference information. The random data output circuit is coupled to the phase difference detection circuit and outputs random data according to the phase difference information. Thereby, ideal and unpredictable random data is generated.

Abstract: A voltage converter and a control circuit thereof are provided. The control circuit includes a voltage status comparator and a control signal generator. The voltage status comparator receives an input voltage and an output voltage, and provides a base voltage. The voltage status comparator compares voltage values of the output voltage and the input voltage or compares voltage values of the output voltage and the base voltage according to a voltage status of the input voltage, and generates a comparison result. The voltage status comparator generates a bias voltage according to the comparison result. The control signal generator generates a control signal according to the bias voltage and transmits the control signal to a control terminal of a driving switch, where the driving switch is turned on or cut off according to the control signal.

Abstract: To provide an inductive load driving device which can control a clamp voltage using a ground voltage as a reference, with a simple structure. An inductive load driving device includes: an inductive load whose one end is connected to a power source and whose other end is connected to a ground: an output stage semiconductor switch element connected in series with the inductive load; a clamping circuit connected between a high-voltage side electrode and a control electrode of the output stage semiconductor switch element; and a resistance value control unit connected between the control electrode of the output stage semiconductor switch element and the ground.

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage.

Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

Abstract: An electric power control system of the present invention is connected to an electric power supplying means for supplying electric power and a load means for accepting supply of electric power and consuming the electric power. The electric power control system includes: a supplied energy acquiring means for acquiring a supplied energy, which is the amount of electric power supplied from the electric power supplying means; a consumed energy acquiring means for acquiring a consumed energy, which is the amount of electric power consumed by the load means; and an electric power supply and demand controlling means for, depending on a total supplied energy as the total of the acquired supplied energy and a total consumed energy as the total of the acquired consumed energy, transmitting and/or receiving electric power to and from another device to change the total supplied energy.

Abstract: A circuit includes a first driver, a second driver, and one or more monitor modules coupled to the first or second driver to measure slope times of the first or second driver. The circuit further includes a comparator coupled to the one or more monitor modules to compare the slope times of the first and second drivers. The circuit further includes one or more regulators coupled to the comparator and the first or second driver to regulate a slope of the first or second driver, based on output of the comparator, at most once per pulse cycle until the slope of the first or second driver reaches a target slope.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: In a boost chopper circuit, a withstand voltage of at least one device of a switching device circuit is lower than a withstand voltage of a capacitor circuit connected in series to a backflow prevention diode circuit between opposite ends of the switching device circuit.

Abstract: The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained second circuit. The second setting (Y) provides a measure of duty cycle of the inverted received signal. The circuits and methods then adjust the duty cycle of the received signal based upon the first and second settings (X, Y) and further retrain of the second circuit to provide an improved duty cycle in a direction closer to 50 percent.

Abstract: A semiconductor package includes a VLSI semiconductor die and one or more output circuits connected to supply power to the die mounted to a package substrate. The output circuit(s), which include a transformer and rectification circuitry, provide current multiplication at an essentially fixed conversion ratio, K, in the semiconductor package, receiving AC power at a relatively high voltage and delivering DC power at a relatively low voltage to the die. The output circuits may be connected in series or parallel as needed. A driver circuit may be provided outside the semiconductor package for receiving power from a source and driving the transformer in the output circuit(s), preferably with sinusoidal currents. The driver circuit may drive a plurality of output circuits. The semiconductor package may require far fewer interface connections for supplying power to the die.

Abstract: A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.

Abstract: The present invention provides an apparatus for adding jitters to the edges of a pulse sequence, the pulse sequence which edges is needed to adding jitters to is sent to a first edge-pulse converter and a second edge-pulse converter respectively, and be converted into a rising edge pulse signal and a falling edge pulse signal. The rising edge pulse signal and the falling edge pulse signal are delayed by different fixed times, and for the edge pulse signal which is delayed shorter, it should be further delayed by a programmable delay circuit, thus the edge to which the jitter is added can be adjusted to a leading position or a lagging position according to a jitter data read out from a jitter data storage, so the synthesized pulse sequence with jitter-added edges can be used as test signal for jitter tolerance measurement.

Abstract: A transmitter includes a first resonator to generate an oscillating field at a resonant frequency in response to receiving power from a power source. The transmitter includes a first communication interface and a first controller to control the first resonator and to communicate data via the first communication interface. One of a plurality of receivers includes a second resonator to be wirelessly coupled to the first resonator. The second resonator resonates at the common mode resonant frequency in response to the oscillating field. The one receiver includes a second communication interface to establish wireless side-channel communications with the first communication interface and to communicate the data with the first communication interface via the wireless side-channel communications. The first controller identifies the one receiver from the plurality of receivers according to the communicated data, and in response, the first resonator transfers the power to the second resonator.

Abstract: A power storage device includes an outer casing and two battery units housed in the outer casing. Each battery unit includes a battery casing formed with a top casing and a bottom casing. The battery casing houses a battery block group in which battery lines are arranged in parallel in a direction substantially perpendicular to the battery line extending direction, and are arranged in a stacked straw bag arrangement, wherein the two or more battery units are vertically housed in the outer casing and are stacked in two or more stages in a horizontal direction, the bottom surface portions facing in the horizontal direction.

Abstract: A radio frequency switch apparatus includes a radio frequency switch, a dynamic bias circuit, and a switch control circuit. The radio frequency switch includes a first radio frequency switch circuit connected between a first signal terminal and an input terminal. The first radio frequency switch circuit includes a series switch and a shunt switch. The dynamic bias circuit is configured to generate a bias voltage and a buffer voltage lower than a battery voltage by a preset voltage, using the battery voltage and configured to output the bias voltage to a signal line connected to the input terminal. The switch control circuit is configured to generate first and second gate voltages to switch the first radio frequency switch circuit, based on a band selection signal, using the battery voltage and the buffer voltage.

Abstract: A system and method for wireless resonant power transfer is disclosed. The system may include a transmitter that, in addition to being configured for resonantly coupling power into an oscillating electric and/or magnetic field, is also configured to transmit one or more test signals. Test signals can include single frequency continuous wave test signals, frequency sweep test signals, and time-pulsed modulated test signals. By comparing measurements of phase and amplitude of both the transmitted test signal and one or more reflections of the test signal reflected by one or more reflecting entities, electromagnetic properties of the one or more reflecting entities may be determined. The determined properties may then be used to enhance the efficiency and/or effectiveness of power transfer, and/or to distinguish between legitimate and illegitimate consumption of wirelessly transferred power by devices in the oscillating field.