Patents Examined by Cathy F. Lam
  • Patent number: 5837368
    Abstract: The occurrence of burrs and chips in punching an insulating film is suppressed by adjusting an edge tearing resistance of the insulating film. The edge tearing resistance is preferably 50 to 70 kgf/20 mm for the purpose of suppressing the burrs and the chips.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: November 17, 1998
    Assignee: Hitachi Cable, Ltd.
    Inventors: Toshikatsu Hiroe, Kenichi Kaneko, Noboru Imai, Hiroyuki Takasaka, Toshio Kawamura
  • Patent number: 5837356
    Abstract: A wiring board constructed of an integral combination of an insulating substrate including 60-95% by weight of a powder of an inorganic insulating material and 5-40% by weight of a thermosetting resin which joins the particles of the powder of an inorganic insulating material, and an insulating substrate-coating, wiring conductor which includes 70-95% by weight of a metal powder and 5-30% by weight of a thermosetting resin.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: November 17, 1998
    Assignee: Kyocera Corporation
    Inventors: Naohiro Katori, Kiyoshi Tomita, Fujito Nakakawaji, Yoichi Sekioka, Syogo Matsuo, Koichi Uchimoto
  • Patent number: 5837355
    Abstract: A process for producing a multilayer printed circuit board, comprising the steps of: impregnating a thermosetting resin in a base material to form a prepreg, applying a thermosetting epoxy resin undercoating agent comprising dicyandiamide and a micro-capsulated imidazole compound to at least one side of an interlayer circuit board on at least one side of which circuit has been formed, heating the applied undercoating agent to dry or semi-cure the undercoating agent, and laying the prepreg on at least one side of the dried or semi-cured undercoating agent-applied interlayer circuit board and subjecting them to laminating press.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: November 17, 1998
    Assignee: Sumitomo Bakelite Company Limited
    Inventor: Hiroshi Hayai
  • Patent number: 5834106
    Abstract: A ceramic substrate for a hard disc, a thin film chip capacitor, and hybrid ICs, and a suction carrier for a substrate is constituted by using a titanium oxide or aluminum oxide substrate having an extremely small number of pores having diameters of 3 .mu.m or more on the substrate surface.The substrate is produced by baking highly purified titanium oxide fine powder or highly purified aluminum oxide fine powder in the air, an inert atmosphere or a reducing atmosphere (at 1,100.degree. C. to 1,300.degree. C. for the former and at 1,200.degree. to 1,400.degree. C. for the latter) and HIP treating the baked material.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: November 10, 1998
    Assignee: Nihon Cement Co., Ltd.
    Inventors: Hideto Kamiaka, Yukio Kishi
  • Patent number: 5834101
    Abstract: A metal base board comprising a metal plate, a circuit conductor section, and an insulating layer provided between the circuit conductor and the metal plate wherein the insulating layer comprises an organic insulating material with flaky inorganic fillers added therein and the flaky inorganic fillers are stacked in the insulating layer in a stratified state.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Satoru Hayashi
  • Patent number: 5830563
    Abstract: This invention relates to an interconnection structure comprising one or more insulating films and one or more layers of conductor electrode patterns, wherein at least one of the insulating films consists of a fluorene skeleton-containing epoxy acrylate resin, and to a method of making a multilayer interconnection structure including the steps of roughening the surface of an insulating resin layer and forming a conductor thereon by electroless plating, wherein the average roughness (Ra), maximum roughness (Ry) and conductor thickness (T) of the roughened surface of the insulating resin layer satisfy the following relations:0.2.ltoreq.Ra.ltoreq.0.6 (unit: .mu.m) (1)0.02.ltoreq.Ra/T.ltoreq.0.2 (2)0.05.ltoreq.Ry/T.ltoreq.0.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: November 3, 1998
    Assignee: NEC Corporation
    Inventors: Tadanori Shimoto, Yoshitsugu Funada, Koji Matsui, Yuzo Shimada, Kazuaki Utsumi
  • Patent number: 5827615
    Abstract: A metallized film substrate having a core layer comprising a film-forming base polymer, a metal receiving skin layer of an ethylene vinyl alcohol copolymer (EVOH) on a surface of the core layer, the film substrate containing a metal deposit, e.g., aluminum, on the EVOH copolymer surface, and a polymeric low temperature sealable coating comprising a copolymer of about 10 to 35 wt. % of at least one .alpha.,.beta.-ethylenically unsaturated carboxylic acid with about 65 to 90 wt. % of ethylene, an alkyl acrylate or methacrylate, acrylonitrile, or mixtures thereof, on the surface of said metal deposit. For adhesion of the EVOH, the core layer may either (i) be blended with a maleic anhydride modified polyolefin or (ii) have an adhesion-promoting tie layer of a maleic anhydride-modified polyolefin on a surface which is in contact with the EVOH.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: October 27, 1998
    Assignee: Mobil Oil Corporation
    Inventors: Robert E. Touhsaent, M. Lawrence Tsai
  • Patent number: 5827604
    Abstract: This invention is to provide a multilayer printed circuit board having excellent appearance and reliability and a method of producing the same, and proposes a build-up multilayer printed circuit board comprising an interlaminar insulating layer 4 comprised of an adhesive for additive process between an inner layer copper pattern 3 provided at its surface with a fine uneven layer 9 and an outer layer copper pattern 6 in which the surface of uneven layer 9 in the inner layer copper pattern 3 is covered with a metal layer containing one or more of metals having an ionization tendency not lower than that of copper but not higher than that of titanium, or a noble metal layer 10, and a production technique therefor.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: October 27, 1998
    Assignee: Ibiden Co., Ltd.
    Inventors: Hiroaki Uno, Masato Kawade
  • Patent number: 5827606
    Abstract: In the electrode for preventing noise electric wave according to the present invention in which the resistivity of the second layer is larger than that of the first layer, it is possible to prevent the generation of noise electric wave. In the electrode for preventing noise electric wave according to the present invention in which the layer for preventing noise electric wave has the porosity of not more than 20%, it is possible to prevent the radio noise. In the electrode for preventing noise electric wave according to the present invention in which the high-fusing conductive material layer exists between the substrate and the resisting material layer, it is possible to prevent the formation of the concave portion.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: October 27, 1998
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Ikuo Marumoto, Taisuke Miyamoto, Satoru Tojo, Toshio Asahi, Hiroshi Morita, Iwao Hibino, Kimitoshi Murata, Nobuyuki Ishihara
  • Patent number: 5822856
    Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: October 20, 1998
    Assignee: International Business Machines Corporation
    Inventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
  • Patent number: 5820972
    Abstract: A metal base board comprising a metal plate, a circuit conductor section, and an insulating layer provided between the circuit conductor and the metal plate wherein the insulating layer comprises an organic insulating material with flaky inorganic fillers added therein and the flaky inorganic fillers are stacked in the insulating layer in a stratified state.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: October 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Satoru Hayashi
  • Patent number: 5817406
    Abstract: A ceramic susceptor with an embedded metal electrode. The metal electrode has multiple apertures, and the ceramic material is cross-linked through the apertures. An electrical connection to the electrode protects the electrode from the environment in the processing chamber. The ceramic may be aluminum nitride, and the metal electrode may be a mesh of molybdenum wires. To form the electrical connection, the susceptor may be heated until an eutectic forms between a conductive connector and the metal electrode. Alternately, a brazing material may be placed between the metal layer and a conductive connector.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: October 6, 1998
    Assignee: Applied Materials, Inc.
    Inventors: David W. Cheung, Mark A. Fodor, Christopher Lane, Ryusuke Ushikoshi, Hideyoshi Tsuruta, Tomoyuki Fujii
  • Patent number: 5817404
    Abstract: The present invention provides a printed circuit board in which electrode layers can electrically be connected by an inner-through-hole connection, the coefficient of thermal expansion of the board is equal to that of a semiconductor, high thermal conductivity can be obtained and wiring can be formed at a high density. A cover film is laminated on both surfaces of a resin impregnated fabric sheet, holes are formed by laser beams in the direction of the thickness of the sheet and cover film, an electrically conductive paste that contains the electrically conductive particles and a thermosetting resin is filled in the holes. The cover film is removed, a copper foil is placed on both sides of the sheet, and pressed and heated, and the resin component of the sheet and that of the electrically conductive paste are hardened.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 6, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouji Kawakita, Seiichi Nakatani, Masahide Tsukamoto
  • Patent number: 5817405
    Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Anikumar Chinuprasad Bhatt, Ashwinkumar Chinuprasad Bhatt, Robert Jeffrey Day, Thomas Patrick Duffy, Jeffrey Alan Knight, Richard William Malek, Voya Rista Markovich
  • Patent number: 5814393
    Abstract: A raw material plastic film like a band stretched in two directions with a machine direction as a longitudinal direction of stretch and a transverse direction as a lateral direction of stretch is prepared. One standard line parallel with the machine direction of stretch is assumed on a film face of the raw material plastic film. An area due to cut a cover layer plastic film and an area due to cut a base layer plastic film (the two areas are of almost the same shape) are assumed to be on the standard line in a state in which the areas are aligned in orientation. However, both an arbitrary point of the area due to cut and the point of the area due to cut corresponding thereto need to be on the standard line. A cover layer plastic film and a base layer plastic film are cut out from the two areas due to cut. Metal electric circuit is formed on a surface of the base layer plastic film via an adhesive layer. The metal electric circuit has a plastic deformation component of 0.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: September 29, 1998
    Assignee: Nitto Denko Corporation
    Inventors: Chiharu Miyaake, Toshihiko Sugimoto, Yousuke Miki
  • Patent number: 5814571
    Abstract: A dielectric paste used for fabrication of a capacitor which permits manufacture of a small-sized ceramic oscillator by being incorporated in the oscillator. The dielectric paste comprises powdered glass, dielectric powder, and an organic vehicle. The dielectric powder is a lead-based perovskite compound. The powdered glass includes a main component given by xSiO.sub.2 --yB.sub.2 O.sub.3 --zPbO (where x, y, and z are expressed in mole percent). The x, y, and z lie within a region defined by connecting points A (x=70, y=0, and z=30), B (x=70, y=15, and z=15), C (x=10, y=75, and z=15), and D (x=10, y=0, and z=90). Preferably, at least one member selected from the group consisting of Al.sub.2 O.sub.3, CaO, TiO.sub.2, ZrO.sub.2, BaO and MgO is used as an additive. Preferably, glass frit accounts for about 35-95% by weight of the mixture of the powdered glass and the dielectric powder, and the dielectric powder accounts for about 5-65% by weight.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: September 29, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiromichi Kawakami, Hiroji Tani
  • Patent number: 5807626
    Abstract: A ceramic circuit board is characterized by being constituted by bonding a ceramic substrate 2 and a metal circuit plate 3 to each other through a silver-copper-based brazing material layer 5 containing at least one active metal selected from Ti, Zr, Hf, V, Nb and Ta, and wherein the Vickers hardness of a reaction product layer 6 generated by causing the silver-copper-based brazing material layer 5 and the ceramic substrate 2 to react with each other is 1,100 or more. At least one element selected from In, Zn, Cd, and Sn is preferably contained in the silver-copper-based brazing material layer 5. Further, 0.1 to 10.0 wt % of carbon powder is preferably contained in the brazing material layer 5. According to the above arrangement, there can be provided a ceramic circuit board in which cracks are effectively suppressed from being formed even after a thermal cycle is repeatedly applied for a long period of time, i.e.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: September 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Naba
  • Patent number: 5807793
    Abstract: A description is provided of laminates for printed circuits using unidirectional glass fabric produced with continuous yarn which is twisted, has a low number of twists or zero twisting turns with different gramme weights, interlaced warpwise with a leno interwoven binding using glass yarns of 5.5 to 22 Tex at a spacing of up to 20 cm. The application of these laminates to the manufacture of printed circuits offers advantages in terms of surface roughness and waviness, dimensional stability, evenness and perforability.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: September 15, 1998
    Assignee: Gividi Italia S.p.A.
    Inventors: Diego Armando Scari, Marco Scari
  • Patent number: 5800932
    Abstract: Disclosed is an electric contact material which comprises a contact substrate and a coating layer formed integrally on the surface of the contact substrate. The coating layer is formed of an Ag-Li-La alloy containing Au or/and Pd, and has a surface layer portion formed as a concentration gradient layer whose Au or/and Pd content decreases as a subsurface portion is approached. The Au or/and Pd concentration of the surface of the surface layer portion ranges from 50 to 95% by weight. The contact material is manufactured by forming an Au or/and Pd layer on the Ag-Li-La alloy and then heat-treating the whole resulting structure, thereby thermally diffusing the Au or/and Pd. This electric contact material has excellent corrosion resistance and lubricity, and its contact resistance changes little with time.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: September 1, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Satoshi Suzuki, Mitsuru Murakawa
  • Patent number: 5780173
    Abstract: The durability and reliability of a polymer layer/metal layer sensor structure is improved by the incorporation of a metal oxide, e.g., tantalum oxide (Ta.sub.2 O.sub.5), layer between the polymer, e.g., polyimide, and the metal, e.g., platinum. sensor element.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: July 14, 1998
    Assignee: General Motors Corporation
    Inventors: Charles Robert Harrington, Marie Irene Harrington, Michel Farid Sultan, John Richard Troxell