Abstract: A circuit board (A1) includes an insulative substrate (1), a conductive pad (4a) formed on the substrate, and a metal (3) bonded to the pad via a solder layer (6). The metal piece (3) has a welding portion (3a) to which an external-connection terminal (5) is welded. A gap (7) is provided between the welding portion (3a) and the substrate (1). The welding portion (3a) and the solder layer (6) are separated by the gap (7).
Abstract: A solvent-free filling material comprising a filler, a thermosetting resin, a curing agent, and a curing catalyst, wherein the thermosetting resin is an epoxy resin, and the curing agent is a dicyandiamide curing agent; a multilayer printed wiring board comprising a substrate, a through-hole, the filling material filling the through-hole, and a conductor layer formed on an exposed surface of the filling material in the through-hole; and a process for producing the multilayer printed wiring board.
Abstract: A multi-layer structure whose volume changes when a temperature exceeds a predetermined threshold value, a microscopic structure drawing method that involves emitting a laser beam onto the multi-layer structure to create a temperature distribution within a beam spot and performing microscopic recording on a portion of the beam spot having a temperature higher than the threshold value, an optical disc master, and a mastering method using the same, where the multi-layer structure includes a substrate and a transformation layer formed on the substrate, wherein a volume of a portion of the transformation layer irradiated by a laser beam changes when the temperature of the portion exceeds a predetermined temperature. The microscopic structure drawing method includes emitting the laser beam onto a predetermined region of the transformation layer and heating the region of the transformation layer irradiated by the laser beam beyond a predetermined temperature so that the heated region can undergo a volume change.
Type:
Grant
Filed:
May 20, 2004
Date of Patent:
October 14, 2008
Assignees:
Samsung Electronics Co., Ltd., National Institute of Advanced Industrial Science and Technology
Inventors:
Joo-ho Kim, In-sik Park, Masashi Kuwahara, Junji Tominaga, Takayuki Sima
Abstract: A counterfeit-proof metal foil is textured in at least a given partial area of its surface, this partial area having a radiation refraction value which is different compared to the remaining surface area. The metal foil is suitable as a packaging material, among others for medications. The manufacturer or the consumer can check based on the given surface structure which is intended as an identification sign whether he has acquired an uncounterfeited product. If texturing takes place on most of the surface of the metal foil, this is identical to the appearance of a printed picture so that the metal foil as claimed in the invention is likewise used as a decorative foil or an advertizing medium.
Type:
Grant
Filed:
November 25, 2005
Date of Patent:
September 30, 2008
Assignee:
Teich Aktiengesellschaft
Inventors:
Engelbert Scharner, Helmut Kloss, Adolf Schedl, Wilhelm Zuser, Lambert Nekula
Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.
Type:
Grant
Filed:
February 26, 2007
Date of Patent:
September 9, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Tae S. Kim, Jin Zhao, Nathan J. Kruse, August J. Fischer, Ralf B. Willecke
Abstract: The present invention provides a multilayer printed wiring board having a filled viahole structure advantageously usable for forming a fine circuit pattern thereon, and having an excellent resistance against cracking under a thermal shock or due to heat cycle. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers each having formed through them holes each filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 ?m.
Abstract: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.
Abstract: The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate through the PMOS transistor during the ESD event.
Abstract: A method of making algae-resistant shingles in which the algae-inhibiting material, usually a copper compound, is applied only to larger granules, instead of being applied to a full size range of granules. Use of the larger granules only, as algae-resistant granules, significantly increases the percentage of surface area of algae-resistant granules for releasing algae-inhibiting material and also reduces the material consumption of the algae-inhibiting material during production of the algae-resistant granules, thus substantially reducing cost.
Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.
Type:
Grant
Filed:
June 8, 2001
Date of Patent:
September 25, 2007
Assignee:
Picogiga International SAS
Inventors:
Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
Abstract: A circuit board for a liquid discharging apparatus in which coating performance of a protective layer and a cavitation resistive film on a heat generating element is excellent and durability is excellent and a manufacturing method of such a circuit board are provided. A surface portion of a wiring material layer is processed so that an etching speed of the surface portion is made higher than that of the material forming the wiring material layer. It is desirable to execute a process for forming at least one selected from a fluoride, a chloride, and a nitride of the material forming the wiring material layer into the surface portion of the wiring material layer.
Type:
Grant
Filed:
October 21, 2004
Date of Patent:
September 18, 2007
Assignee:
Canon Kabushiki Kaisha
Inventors:
Keiichi Sasaki, Masato Kamiichi, Ershad Ali Chowdhury, Yukihiro Hayakawa
Abstract: A flocked substrate that can be printed in non-impact printers and photocopiers, including bubble jet, piezoelectric and LaserJet printers, a method of printing on flocked substrate using that flocked substrate, and a jigsaw puzzle made using the printed flocked substrate, with an adhesive backing.
Abstract: The present invention is directed to a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects.
Type:
Grant
Filed:
February 16, 2005
Date of Patent:
June 12, 2007
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
Abstract: The present invention relates to a Cd-free and Pb-free glass composition comprising, based in mol %, 1–10% MO where M is selected from Ba, Sr, Ca and mixtures thereof, 5–30% MgO, 0.3–5% CuO, 0–2.5% P2O5, 0–2.5% ZrO2, 24–45% ZnO, 2–10% Al2O3, 35–50% SiO2 and 0.1–3% A2O where A is selected from the group of alkali elements and mixtures thereof wherein the glass composition is useful in thick paste dielectric materials which are compatible with AlN substrates.
Abstract: An object of the present invention is to provide a ceramic substrate that is superior in temperature rising/dropping characteristics and breakdown voltage at a high temperature, has a small warp amount, and is best as a substrate for semiconductor-producing/examining devices. The ceramic substrate of the present invention is a ceramic substrate having a conductor formed on the surface thereof or inside thereof, characterized in that said ceramic substrate is having 15×1011 or less pores which have a diameter of 0.5 ?m or more per m2.
Abstract: An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.
Type:
Grant
Filed:
November 8, 2002
Date of Patent:
August 23, 2005
Assignee:
International Business Machines Corporation
Inventors:
Ann R Fornof, Jeffrey C Hedrick, Kang-Wook Lee, Christy S Tyberg
Abstract: The present invention provides a ceramic substrate for use in an apparatus for manufacturing and inspecting semiconductors. The ceramic substrate comprises a through-hole having excellent tolerance performance against a drawing stress applied to an external terminal pin. The through-hole is provided with a projection which protrudes into the ceramic substrate made of aluminum nitride as primary component.
Abstract: The present invention provides a multilayer ceramic composition comprising at least one layer of dielectric material M1 and at least one layer of dielectric material M2, wherein passive components are buried in both layers of dielectric material M1 and M2 that prevent each other from shrinkage in the X and Y dimensions during firing. Each layer of the multilayer ceramic composition according to the invention can be used as a substrate for burying the passive component and has the ability to prevent other layer with different dielectric constant from shrinkage. Hence, the multilayer ceramic composition has the advantages of smaller size and a better circuit precision.
Abstract: Disclosed are fiber reinforced composite substrates comprising a polymeric matrix and one or more woven or non-woven para-aramid or fiberglass fabrics, sheets, or papers, said polymeric matrix consisting essentially of one or more cross-linked copolymers of monovinyl aromatic hydrocarbons and conjugated dienes useful for printed circuit boards and cards suitable for use in high frequency circuits.
Type:
Grant
Filed:
April 25, 2003
Date of Patent:
May 10, 2005
Assignee:
E. I. du Pont de Nemours and Company
Inventors:
Pui-Yan Lin, Govindasamy Paramasivan Rajendran, George Elias Zahr
Abstract: In a composite device having a laminate structure of a magnetic body ceramic layer 1 and a dielectric ceramic layer 2, an intermediate layer 3 is interposed between the ceramic layers 1 and 2. The intermediate layer 3 varies in composition in the direction of thickness thereof and exhibits substantially the same shrinkage as the magnetic body ceramic layer 1 at a joint thereof with this layer 1 when fired and substantially the same shrinkage as the dielectric ceramic layer 2 at a joint thereof with the layer 2 when fired, whereby the ceramic layers can be prevented from cracking or separating during firing.