Patents Examined by Cathy Lam
  • Patent number: 8940998
    Abstract: A free-standing metallic article, and method of making, is disclosed in which the metallic article is electroformed on an electrically conductive mandrel. The mandrel has an outer surface with a preformed pattern, wherein at least a portion of the metallic article is formed in the preformed pattern. The metallic article is separated from the electrically conductive mandrel, which forms a free-standing metallic article that may be coupled with the surface of a semiconductor material for a photovoltaic cell.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: January 27, 2015
    Assignee: GTAT Corporation
    Inventors: Steve Babayan, Robert Brainard, Arvind Chari, Alejandro de la Fuente Vornbrock, Venkatesan Murali, Gopal Prabhu, Venkateswaran Subbaraman, Dong Xu, Arthur Rudin, David Tanner
  • Patent number: 8936748
    Abstract: Artificial turf has a base layer, a multiplicity of blades fixed in and projecting upward from the base layer, and a mass of damping material on the base layer and through which the blades project. Each of the blades is at least partially formed of a polyester of terephthalic acid made from waste. The polyester is polyethylene terephthalate (PET) or polybutylene terephthalate (PBT), both from waste. The base layer is a flat primary layer, preferably a textile and preferably consists of plastic, a polyolefin and/or a polyester of terephthalic acid, preferably a polyester of terephthalic acid from waste.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: January 20, 2015
    Assignee: Reifenhaeuser GmbH & Co. KG Maschinenfabrik
    Inventor: Juergen Morton-Finger
  • Patent number: 8895874
    Abstract: Thin indium-less “optically porous” layers adapted to replace traditional ITO layers are provided herein. A thin metalized film adapted to carry an electrical charge can include a dense pattern of small openings to allow the transmission of light to or from an underlying semiconductor material. The pattern of openings can create a regular or irregular grid pattern of low aspect ratio fine-line metal conductors. Creation of this optically porous metalized film can include the printing of a catalytic precursor material, such as palladium in solution in a pattern on a substrate, drying or curing the catalytic precursor, and the deposition of a thin layer of metal, such as copper on the dried precursor to form the final conductive and optically porous film.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: November 25, 2014
    Assignee: Averatek Corp.
    Inventors: Sunity Kumar Sharma, Alex Newsom Beavers, Jr., Thomas Furst
  • Patent number: 8891225
    Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: November 18, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Nishisaka, Yukio Sanada, Koji Sato, Seiichi Matsumoto
  • Patent number: 8883016
    Abstract: Disclosed is a carrier for manufacturing a printed circuit board, which includes a first carrier including a first binder having a first opening and a first metal layer formed in the first opening of the first binder, and a second carrier, stacked with the first carrier and including a second binder having a second opening and a second metal layer which is formed in the second opening of the second binder and which partially overlaps with the first metal layer, so that the carrier is simply configured and the binders are formed not only on the lateral surfaces of the metal layers but also on the upper surfaces thereof, thus improving the reliability of bonding of the carrier at the periphery. A method of manufacturing the carrier and a method of manufacturing a printed circuit board using the carrier are also provided.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Inventors: Jae Joon Lee, Jin Yong Ahn, Suk Hyeon Cho, Ki Hwan Kim, Seok Kyu Lee
  • Patent number: 8870579
    Abstract: An elastomeric material includes an elastomeric matrix having one or more outer surfaces and a set of electrically conductive pathways disposed through the elastomeric matrix. The elastomeric material also includes a thermally-conductive and electrically-insulative material, disposed through the elastomeric matrix, which improves the formation of the electrically conductive pathways.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Paricon Technologies Corporation
    Inventors: Roger E. Weiss, Clifford Read, Everett Simons
  • Patent number: 8866300
    Abstract: Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Nuvotronics, LLC
    Inventors: David W. Sherrer, James R. Reid, Jr.
  • Patent number: 8865298
    Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature. The resulting article has a substrate on which a reverse composite of the metal grid and electronically conductive polymer is disposed, which article can be incorporated into various devices.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 21, 2014
    Assignee: Eastman Kodak Company
    Inventors: Debasis Majumdar, Roger Lee Klaus, Michael J. Corrigan
  • Patent number: 8852754
    Abstract: Provided is an industrially excellent surface-treated copper foil which satisfies requirements for adhesiveness to an insulating resin such as polyimide, heat-resistant adhesiveness, chemical resistance and soft etching properties. Also provided is a method for producing a surface-treated copper foil which achieves a high adhesion strength between an insulating resin and the copper foil, shows high chemical resistance in circuit formation and sustains good soft etching properties after forming vias by laser-processing. A base copper foil is subjected to a roughening treatment to give a surface roughness (Rz) of 1.1 ?m or below. On the roughened surface, an Ni—Zn alloy layer is formed. The aforesaid roughening treatment is conducted in such a manner that the roughened surface comprises sharp-pointed convexes, which have a width of 0.3-0.8 ?m, a height of 0.6-1.8 ?m and an aspect ratio of 1.2-3.5, and the surface roughness (Rz) of said base copper foil is increased by 0.05-0.3 ?m.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Satoshi Fujisawa, Takeo Uno, Koichi Hattori
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Patent number: 8842413
    Abstract: There is provided a multilayered ceramic electronic component having a reduced thickness and exhibiting hermetic sealing. In multilayered ceramic electronic component, an external electrode includes two layers, that is, first and second layers, and the first and second layers contain glass with different compositions, respectively. Therefore, the multilayered ceramic electronic component having high reliability, such as strong adhesion between the external electrode and the internal electrode, prevention of glass exudation, or the like, may be obtained.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Jun Park, Da Young Choi, Byong Gyun Kim, Ji Sook Kim, Byung Jun Jeon, Hyun Hee Gu, Kyu Ha Lee, Gun Jung Yoon, Eun Sang Na
  • Patent number: 8828555
    Abstract: The present invention is directed to a method for forming a patterned conductive film, which comprises the step of bringing a substrate having a layer made of platinum microcrystal particles formed thereon in a pattern and a complex of an amine compound and an aluminum hydride into contact with each other at a temperature of 50 to 120° C. According to the present invention, there is provided a method for forming a patterned conductive layer, which can ensure electrical bonding with a substrate and also can be suitably applied to various electronic devices, simply without requiring a massive and heavy apparatus.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 9, 2014
    Assignees: Japan Science and Technology Agency, JSR Corporation
    Inventors: Tatsuya Shimoda, Yasuo Matsuki, Zhongrong Shen
  • Patent number: 8822036
    Abstract: Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 2, 2014
    Assignee: UT-Battelle, LLC
    Inventor: Andrew A. Wereszczak
  • Patent number: 8808873
    Abstract: In an embodiment of the invention, a method for manufacturing a carrier-attached copper foil is provided. The method includes providing a carrier foil including stainless steel, titanium, aluminum, nickel or alloy thereof with a surface oxide layer, and forming a copper foil onto the carrier foil to prepare the carrier-attached copper foil.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 19, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Chung Chen, Yi-Ling Lo, Hung-Kun Lee, Tzu-Ping Cheng
  • Patent number: 8777638
    Abstract: A wiring board includes a first substrate portion including a first feed-through conductor portion in a vertical direction, a second substrate portion provided on the first substrate portion and including a second feed-through conductor portion in a vertical direction of a corresponding part to the first feed-through conductor portion, and a feed-through electrode including the first feed-through conductor portion and the second feed-through conductor portion.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 15, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Akinori Shiraishi, Mitsutoshi Higashi
  • Patent number: 8759986
    Abstract: Provided is a substrate structure including: a base substrate on which a conductive pattern is formed; a first plating layer covering the conductive pattern; and a second plating layer covering the first plating layer, wherein the first plating layer includes an electroless reduction plating layer.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 24, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chul Min Lee, Won Hyung Park, Kyung Jin Heo, Dek Gin Yang, Jin Su Yeo, Sung Wook Chun
  • Patent number: 8754328
    Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface covers the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: June 17, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Jun-Chung Hsu, Chi-Ming Lin, Tso-Hung Yeh, Ya-Hsiang Chen
  • Patent number: 8746308
    Abstract: In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Patent number: 8734934
    Abstract: A surface metal film material including, in this order, a substrate, a polymer layer that receives a plating catalyst or a precursor thereof, and a metal film formed by plating, wherein, when x ?m represents surface roughness (Ra) at the interface between the substrate and the polymer layer, and y ?m represents surface roughness (Ra) at the interface between the polymer layer and the metal film, x>y and 5 ?m>x>0.1 ?m, and wherein, when T ?m represents a thickness of the polymer layer, T and x satisfy the relationship 2x?T.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: May 27, 2014
    Assignee: FUJIFILM Corporation
    Inventor: Masataka Satou
  • Patent number: 8730646
    Abstract: A laminated electronic component includes outer terminal electrodes including lower plating films including metal particles having an average size of 0.5 ?m or less, the lower plating films being formed by directly plating an outer surface of an electronic component body such that the lower plating films are electrically connected to exposed portions of inner conductors. The outer terminal electrodes may further include upper plating films formed on the lower plating films, the upper plating films being defined by one or more layers. Metal particles defining the upper plating films may have an average size of 0.5 ?m or less. The metal particles defining the lower plating films may be Cu particles.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: May 20, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Kawasaki, Shunsuke Takeuchi, Akihiro Motoki, Makoto Ogawa, Toshiyuki Iwanaga