Abstract: A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer in order to emit various colored lights including white light. The semiconductor light-emitting device can include a base board, a frame located on the base board, at least one light-emitting chip mounted on the base board, the wavelength converting layer located between an optical plate and each outside surface of the chips so as to extend toward the optical plate using a meniscus control structure, and a reflective material layer disposed at least between the frame and both side surfaces of the wavelength converting layer and the optical plate. The semiconductor light-emitting device can be configured to improve light-emitting efficiency and color variability between the light-emitting chips by using the reflective material layer as each reflector, and therefore can emit a wavelength-converted light having a high light-emitting efficiency from various small light-emitting surfaces.

Abstract: A semiconductor light emitting diode (LED) and a manufacturing method thereof are disclosed. The method for manufacturing a semiconductor light emitting diode (LED) includes: forming a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a substrate with prominences and depressions; removing the substrate from the light emission structure to expose a first concavoconvex portion corresponding to the prominences and depressions; forming a protection layer on the first concavoconvex portion; removing a portion of the protection layer to expose a convex portion of the first concavoconvex portion; and forming a second concavoconvex portion on the convex portion of the first concavoconvex portion.

Abstract: A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Abstract: An organic electroluminescent element includes a pair of electrodes formed of a positive electrode and a negative electrode, with at least one of the electrodes being transparent or semi-transparent, and one or more organic compound layers interposed between the pair of electrodes, with at least one layer containing one or more charge transporting polyesters represented by the following formula (I), wherein A1 represents at least one selected from structures represented by the following formula (II), and X represents a group represented by the following formula (III):

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: To provide a storage device in which advantages of both a nonvolatile storage device and a volatile storage device can be obtained, a semiconductor device includes a first transistor provided in or over a substrate and a second transistor provided above the first transistor, where at least part of the first transistor and the second transistor are overlapped with each other, and a gate electrode of the first transistor and a source or drain electrode of the second transistor are electrically connected to each other. It is preferable that the first transistor be provided using single crystal silicon and the second transistor be provided using an oxide semiconductor having extremely low off-state current.

Abstract: The present invention provides a solid-state imaging device comprising: a semiconductor substrate having a pixel region and a peripheral circuit region; a multilayer wiring layer including layers of wiring and an interlayer film interposed therebetween, and disposed above the semiconductor substrate to cover the pixel region and the peripheral circuit region except areas above the photoelectric conversion elements; a waveguide member filling the areas above the photoelectric conversion elements (waveguides) and covering the multilayer wiring layer at least within the pixel region; and an optical structure (composed of a color filter material and a lens material) disposed above the waveguide member within the pixel region, wherein a groove is formed by removing a portion of the waveguide member from an area within the pixel region that is in a border between the pixel region and the peripheral circuit region.

Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first dielectric layer over a part of an upper surface of the light emitting structure, and a pad electrode over the first dielectric layer.

Abstract: An organic light-emitting display device that is transparent and prevents distortion of an image transmitted therethrough by preventing light from scattering during image display. The organic light-emitting display device comprises a plurality of pixels, in which each pixel includes a light transmission area, a light emitting area, and a light absorption area. The light transmission area is configured to pass visible light incident thereto. The light absorption is configured to absorb visible light incident thereto.

Abstract: The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar.