Patents Examined by Chandra Chaudhari
  • Patent number: 10770573
    Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 8, 2020
    Assignees: TOWER SEMICONDUCTOR LTD., RAMOT AT TEL AVIV UNIVERSITY LTD.
    Inventors: Zohar Shaked, Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
  • Patent number: 10763255
    Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 10741576
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Akio Nishida
  • Patent number: 10739209
    Abstract: Carbon nanotube-based multi-sensors for packaging applications and methods to form the carbon nanotube-based multi-sensors are capable of simultaneously measuring at least two measurands including temperature, strain, and humidity via changes in its electrical properties.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Duchesne, Dominique Drouin, Hélène Frémont, Simon Landry, Aurore F. M. E. Quelennec, Umar Shafique, Patrick R. J. Wilson
  • Patent number: 10720400
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 10720444
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Kiyohiko Sakakibara
  • Patent number: 10707131
    Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Soon Lim, Zi-Wei Fang
  • Patent number: 10707248
    Abstract: In one general aspect, the techniques disclosed here feature an imaging device that includes: a semiconductor substrate; a first pixel cell including a first photoelectric converter in the semiconductor substrate, and a first capacitive element one end of which is electrically connected to the first photoelectric converter; and a second pixel cell including a second photoelectric converter in the semiconductor substrate. An area of the second photoelectric converter is larger than an area of the first photoelectric converter in a plan view.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 7, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sanshiro Shishido, Masashi Murakami, Kazuko Nishimura
  • Patent number: 10700277
    Abstract: A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10692946
    Abstract: An organic electroluminescence (EL) display panel includes pixels arranged in a matrix of rows and columns, and includes: a substrate; pixel electrode layers that are arranged on the substrate in the matrix; an insulating layer that is provided above the substrate and the pixel electrode layers, and has elongated openings and a grooved portion for each of the pixels, the openings extending in a column direction and being arranged in a row direction, the grooved portion having an upper opening and a bottom and being communicated with at least one of the openings in plan view; organic functional layers that are provided above the pixel electrode layers, and include light emitting layers in which organic electroluminescence occurs in the openings; and a light-transmissive counter electrode layer that is provided above the organic functional layers. Cross-sectional profiles of the openings taken along the row direction are uniform in the column direction.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 23, 2020
    Assignee: JOLED INC.
    Inventors: Jiro Yamada, Kazuma Teramoto, Kenichi Nendai, Kaoru Abe, Hideki Kobayashi, Hirotaka Nanno
  • Patent number: 10692762
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10680052
    Abstract: An organic light-emitting display and a method of manufacturing the same are provided. An organic light-emitting display includes: a substrate including a light-emission region and a non-light-emission region around the light-emission region; a display device on the light-emission region of the substrate; and an encapsulation member on the display device. The encapsulation member includes a light-shielding member including a first light-shielding layer and a second light-shielding layer, the first light-shielding layer being in a region corresponding to the non-light-emission region, and the second light-shielding layer being on the first light-shielding layer; and a color conversion member in a region corresponding to the light-emission region.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyeonbum Lee, Hyoengki Kim, Jeongwon Kim, Kwangwoo Park, Junhyuk Woo, Jihwang Lee
  • Patent number: 10658511
    Abstract: The present disclosure is directed to a semiconductor device and a manufacturing method therefor. In one implementations, a method includes: providing a semiconductor structure, where the semiconductor structure includes: a substrate, and a first fin and a second fin spaced on the substrate; depositing a first interlayer dielectric layer on the semiconductor structure; performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin; after the top of the first fin is exposed, removing a part of the first fin to form a first groove; epitaxially growing a first electrode in the first groove; performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin; after the top of the second fin is exposed, removing a part of the second fin to form a second groove, where the second groove is separated from the first groove; and epitaxially growing a second electrode in the second groove.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Yong Li
  • Patent number: 10636700
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Mohit K. Haran, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan
  • Patent number: 10629588
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Patent number: 10629683
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concertation than the dopant concentration in the second well.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Doug Weiser
  • Patent number: 10622586
    Abstract: An organic light-emitting display apparatus is provided. The display apparatus includes a pixel-defining layer disposed on a substrate, wherein the pixel-defining layer defines an emission region and a non-emission region, an organic light-emitting device disposed in the emission region, and a protruding portion disposed on a portion of the pixel-defining layer in the non-emission region. The display apparatus also includes a thin film encapsulating layer disposed on the substrate for sealing the organic light-emitting device and the protruding portion, the thin film encapsulating layer comprising at least one organic film and at least one inorganic film, wherein at least one organic film corresponds to a functional organic film, and a height of a first upper surface of the functional organic film disposed away from the protruding portion is lower than a height of a second upper surface of the functional organic film disposed near a top of the protruding portion.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 10622465
    Abstract: A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Xia Li, Bin Yang
  • Patent number: 10622397
    Abstract: A semiconductor layer includes an opening, and in a joint surface between structures, a portion between a semiconductor layer and an opening in a direction in which the semiconductor layers are stacked together includes a plurality of conductor portions and an insulator portion located between the plurality of conductor portions in a direction orthogonal to the direction.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 14, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideaki Ishino, Takumi Ogino
  • Patent number: 10605989
    Abstract: A method of manufacturing an integrated semiconductor optical waveguiding device comprising an elongated waveguide, the method comprising: providing a material stack comprising a substrate layer, an anisotropically wet etchable conductive layer, a waveguiding core layer, an etch-guiding layer between the substrate layer and the waveguiding core layer, and InP material between the etch-guiding layer and the waveguiding core layer; etching said material stack down to and including said waveguiding core layer, to form an elongated shape of the elongated waveguide together with an etched area laterally beside the waveguide; providing an etch mask material across the formed waveguide; and wet etching parts of said etched areas that are not protected by the etch mask, to remove material of the etch-guiding layer across a lateral direction of the waveguide, forming a laterally extending through tunnel in the etch-guiding layer and in the conductive layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 31, 2020
    Assignee: Finisar Sweden AB
    Inventors: David Adams, Martin Anders Isak Stattin, Christopher Daunt