Patents Examined by Chandra Chaudhari
  • Patent number: 10388620
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Patent number: 10381435
    Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Patent number: 10373963
    Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen, Ying-Yan Chen, Jeng-Ya David Yeh
  • Patent number: 10359676
    Abstract: A display device including a substrate, a gate line, a data line, a plurality of thin film transistors, a first pixel electrode, and a second pixel electrode. The gate line is disposed on the substrate. The data line is disposed on the substrate. The data line includes a first branch line and a second branch line. The first branch line and the second branch line form a closed loop. The plurality of thin film transistors is connected to the data line. The first pixel electrode is connected to at least one of the plurality of thin film transistors. The second pixel electrode is connected to at least another one of the plurality of thin film transistors. The first pixel electrode and the second pixel electrode are arranged in a substantially diagonal direction with respect to each another. The first branch line is connected to a source electrode of said at least one of the plurality of thin film transistors.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hwanyoung Jang, Kyunghoe Lee, Seongyoung Lee, Byoungsun Na, Seonkyoon Mok, Hyungjun Park
  • Patent number: 10347662
    Abstract: The present disclosure discloses an array substrate comprising: a substrate; a gate electrode; a gate insulating layer formed on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode; an active layer formed on one side of the gate insulating layer away from the gate electrode and made of an indium gallium zinc tin oxide material; an ohmic contact layer formed on one side of the active layer away from the gate insulating layer and made of a conductive indium gallium zinc oxide material, the ohmic contact layer covering both ends of the active layer; and a source electrode and a drain electrode formed on one side of the ohmic contact layer away from the active layer, the source electrode and the drain electrode being electrically connected to both ends of the active layer by the ohmic contact layer, respectively.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiaobo Hu
  • Patent number: 10347583
    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Guillaume Bouche
  • Patent number: 10340152
    Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Hung-Yu Chou, Fu-Kang Lee, Steven Alfred Kummerl
  • Patent number: 10340272
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Shou-Wei Hsieh, Hsin-Yu Chen
  • Patent number: 10319625
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Mohit K. Haran, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan
  • Patent number: 10319859
    Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, JinBum Kim, Kang Hun Moon, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Yang Xu
  • Patent number: 10308504
    Abstract: A method of manufacturing and using micro assembler systems are described. A method of manufacturing includes disposing a first plurality of electrodes above a first zone of the substrate, wherein the first plurality of electrodes has a first range of spacing. The method further includes disposing a second plurality of electrodes above a second zone of the substrate, wherein the second plurality of electrodes has a second range of spacing that is less than the first range of spacing. A method of using micro assembler systems includes disposing a mobile particle at least partially submersed in an assembly medium above a substrate, a first plurality of electrodes and a second plurality of electrodes. The method further includes conducting a field through individual electrodes of the first plurality of electrodes and the second plurality of electrodes to generate electrophoretic forces or dielectrophoretic forces on the mobile particle.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jeng Ping Lu, Eugene M. Chow, David K. Biegelsen, Sourobh Raychaudhuri
  • Patent number: 10312080
    Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Ching-Hsiang Chang, Jui-Min Lee, Chia-Lung Chang, Tzu-Chin Wu, Shih-Fang Tzou
  • Patent number: 10310344
    Abstract: A measuring method and a liquid crystal display panel are provided. The measuring method includes disposing a test electrode on an outside of the liquid crystal display panel, and electrically connecting the test electrode with a pixel electrode, and measuring a voltage of the pixel electrode by the test electrode when the liquid crystal display panel is in operation. The voltage of the pixel electrode can be directly measured by the measuring method, thereby increasing the accuracy for measuring the driving voltage of liquid crystal.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: June 4, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Xiong
  • Patent number: 10276621
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 10263075
    Abstract: Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10249631
    Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 2, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chien-Sheng Su, Feng Zhou, Jeng-Wei Yang, Hieu Van Tran, Nhan Do
  • Patent number: 10249435
    Abstract: The invention relates to an electronic component. The electronic component 2 has an electrical assembly 3 having two electrical connections 4, 5 that are each formed on opposing faces of the assembly. For each connection 4, 5, the component has at least one electrically conductive connection element 9, 10 having a mounting foot 14, 15 for connection to a circuit carrier 22. According to the invention, the connection element 8, 9 has at least two metal layers 10, 11, 12, 13 at least on one section, wherein the metal layers are each formed from different metals and integrally connected to one another. Preferably, one metal layer 12, 13 from the metal layers has greater thermal conductivity than the other metal layer 10, 11.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Peuser
  • Patent number: 10243073
    Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang
  • Patent number: 10229961
    Abstract: A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a thin film transistor provided on a first side of the substrate; a first electrode connected with the thin film transistor; an organic emission layer provided on the first electrode and emitting light; a second electrode provided on the organic emission layer; and a light blocking layer contacting the substrate from a second side that faces the first side of the substrate, wherein the light is emitted in a direction toward the second electrode from the organic emission layer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Wan Choi, Young Bin Kim
  • Patent number: 10229975
    Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe