Abstract: A method of manufacturing an integrated semiconductor optical waveguiding device comprising an elongated waveguide, the method comprising: providing a material stack comprising a substrate layer, an anisotropically wet etchable conductive layer, a waveguiding core layer, an etch-guiding layer between the substrate layer and the waveguiding core layer, and InP material between the etch-guiding layer and the waveguiding core layer; etching said material stack down to and including said waveguiding core layer, to form an elongated shape of the elongated waveguide together with an etched area laterally beside the waveguide; providing an etch mask material across the formed waveguide; and wet etching parts of said etched areas that are not protected by the etch mask, to remove material of the etch-guiding layer across a lateral direction of the waveguide, forming a laterally extending through tunnel in the etch-guiding layer and in the conductive layer.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.

Abstract: A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.

Abstract: Provided is a light-emitting element including a first electrode, a partition wall covering an edge portion of the first electrode, a light-confining layer in contact with a side surface of the partition wall and the first electrode, an electroluminescence layer over the first electrode and in contact with the first electrode and the light-confining layer, and a second electrode over the electroluminescence layer. A refractive index of the light-confining layer is lower than a refractive index of the electroluminescence layer.

Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a diffusing step of heating the wafer after performing the coating step, thereby diffusing the metal salt on the back side of the wafer to form a gettering layer containing the metal salt on the back side of the wafer, in which the metal salt is diffused in the gettering layer.

Abstract: A conductive pattern includes an organic insulating layer, a first conductive layer provided on the insulating layer and including at least a first sub-conductive layer, and an additional conductive layer provided between the insulating layer and the first conductive layer, or on the first conductive layer, wherein the additional conductive layer includes a metal nitride.

Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a drying step of drying the wafer after performing the coating step, thereby forming a gettering layer containing the metal salt on the back side of the wafer.

Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.

Abstract: The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: In one embodiment, an electronic display includes a first plurality of hexagon-shaped pixels and a second plurality of hexagon-shaped pixels that are coplanar with the first plurality of hexagon-shaped pixels. The first plurality of hexagon-shaped pixels each include an infrared (IR) emitter subpixel that is operable to emit IR light. The second plurality of hexagon-shaped pixels each include an IR detector subpixel that is operable to detect IR light. Each IR emitter subpixel and each IR detector subpixel includes an anode layer and a cathode layer. Each particular IR emitter subpixel includes an IR emissive layer located between the anode layer and the cathode layer of the particular IR emitter subpixel. Each particular IR detector subpixel includes an IR detector layer located between the anode layer and the cathode layer of the particular IR detector subpixel.

Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside, to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.

Abstract: A method of making a display device, the method including fabricating a matrix of light-emitting diodes (LEDs), each including electrodes accessible from a back face of the matrix and light-emitting surfaces accessible from a front face of the matrix; securing, onto the back face of the matrix, a stack of layers including at least one semiconducting layer, a gate dielectric layer, and a layer of gate conducting material; and starting from the stack of layers, fabricating an electronic control circuit electrically coupled to the electrodes, including fabricating field-effect transistors (FETs) including active zones and gates, the active zones being formed in the at least one semiconducting layer, and the gates being formed in the gate dielectric layer and in the layer of gate conducting material.

Abstract: A semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3A, 3B) which includes a channel region (31A, 31), a high-concentration impurity region, and a low-concentration impurity region (32A, 32B) which is located between the channel region and the high-concentration impurity region, a gate electrode (7A, 7B) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8A, 8B) and a drain electrode (9A, 9B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8A, 8B) and the drain electrode (9A, 9B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at a