Patents Examined by Chandra Chaudhari
  • Patent number: 10608099
    Abstract: A method of manufacturing a semiconductor device includes: etching a plurality of trenches to a first depth in a semiconductor substrate; doping a region of the semiconductor substrate surrounding a bottom of the trenches at the first depth to form a doped region in the semiconductor substrate; after the doped region is formed, etching the plurality of trenches deeper into the semiconductor substrate to a second depth greater than the first depth, adjacent ones of the trenches being separated from one another by a semiconductor mesa; and forming a body region above the doped region in the semiconductor mesas.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: March 31, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Alim Karmous
  • Patent number: 10593794
    Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10580966
    Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Patent number: 10580684
    Abstract: A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Wallner, Katherina Babich, Sunil Kumar Singh
  • Patent number: 10573642
    Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10566349
    Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10566231
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
  • Patent number: 10553657
    Abstract: Provided is a light-emitting element including a first electrode, a partition wall covering an edge portion of the first electrode, a light-confining layer in contact with a side surface of the partition wall and the first electrode, an electroluminescence layer over the first electrode and in contact with the first electrode and the light-confining layer, and a second electrode over the electroluminescence layer. A refractive index of the light-confining layer is lower than a refractive index of the electroluminescence layer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 4, 2020
    Assignee: Japan Display Inc.
    Inventor: Nobuto Managaki
  • Patent number: 10546758
    Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a diffusing step of heating the wafer after performing the coating step, thereby diffusing the metal salt on the back side of the wafer to form a gettering layer containing the metal salt on the back side of the wafer, in which the metal salt is diffused in the gettering layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Daigo Shitabo, Seiji Harada, Hiroki Takeuchi
  • Patent number: 10541149
    Abstract: A gettering layer forming method includes a coating step of applying a solution of metal salt to a back side of a wafer, and a drying step of drying the wafer after performing the coating step, thereby forming a gettering layer containing the metal salt on the back side of the wafer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 21, 2020
    Assignee: DISCO CORPORATION
    Inventor: Seiji Harada
  • Patent number: 10542621
    Abstract: A conductive pattern includes an organic insulating layer, a first conductive layer provided on the insulating layer and including at least a first sub-conductive layer, and an additional conductive layer provided between the insulating layer and the first conductive layer, or on the first conductive layer, wherein the additional conductive layer includes a metal nitride.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hoon Song, Hyun Chul Son, Young Je Shin, Kyong Hun Cho, Jeong Bai Choi
  • Patent number: 10541187
    Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
  • Patent number: 10529664
    Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10522619
    Abstract: The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinyuan Lin, Ying Jin
  • Patent number: 10510812
    Abstract: In one embodiment, an electronic display includes a first plurality of hexagon-shaped pixels and a second plurality of hexagon-shaped pixels that are coplanar with the first plurality of hexagon-shaped pixels. The first plurality of hexagon-shaped pixels each include an infrared (IR) emitter subpixel that is operable to emit IR light. The second plurality of hexagon-shaped pixels each include an IR detector subpixel that is operable to detect IR light. Each IR emitter subpixel and each IR detector subpixel includes an anode layer and a cathode layer. Each particular IR emitter subpixel includes an IR emissive layer located between the anode layer and the cathode layer of the particular IR emitter subpixel. Each particular IR detector subpixel includes an IR detector layer located between the anode layer and the cathode layer of the particular IR detector subpixel.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 17, 2019
    Assignee: Lockheed Martin Corporation
    Inventors: Mark A. Lamkin, Kyle M. Ringgenberg, Jordan D. Lamkin
  • Patent number: 10510763
    Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Ming Wu, Wei-Cheng Wu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai, Ru-Liang Lee, Harry Hak-Lay Chuang
  • Patent number: 10490522
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside, to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 10473709
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Patent number: 10468436
    Abstract: A method of making a display device, the method including fabricating a matrix of light-emitting diodes (LEDs), each including electrodes accessible from a back face of the matrix and light-emitting surfaces accessible from a front face of the matrix; securing, onto the back face of the matrix, a stack of layers including at least one semiconducting layer, a gate dielectric layer, and a layer of gate conducting material; and starting from the stack of layers, fabricating an electronic control circuit electrically coupled to the electrodes, including fabricating field-effect transistors (FETs) including active zones and gates, the active zones being formed in the at least one semiconducting layer, and the gates being formed in the gate dielectric layer and in the layer of gate conducting material.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 5, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Ivan-Christophe Robin, Hubert Bono, Maud Vinet
  • Patent number: 10468533
    Abstract: A semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3A, 3B) which includes a channel region (31A, 31), a high-concentration impurity region, and a low-concentration impurity region (32A, 32B) which is located between the channel region and the high-concentration impurity region, a gate electrode (7A, 7B) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8A, 8B) and a drain electrode (9A, 9B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8A, 8B) and the drain electrode (9A, 9B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at a
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 5, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hiroshi Aichi