Abstract: A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A method of manufacturing a light emitting diode package comprises steps of: scanning a light emitting diode chip mounted on a package substrate to acquire mounting image data; generating three dimensional (3D) image data by comparing the mounting image data with mounting reference data; and forming an optical structure including a plurality of layers on the package substrate on using the 3D image data.

Abstract: A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.

Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, an insulating section, and a semiconductor section. The second semiconductor region is provided on the first semiconductor region. A carrier concentration of the first conductivity type of the second semiconductor region is lower than a carrier concentration of the first conductivity type of the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating section is provided around the first semiconductor region and the second semiconductor region. The insulating section is in contact with the second semiconductor region. The semiconductor section is provided around the insulating section. The semiconductor section is not in contact with the first semiconductor region.

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Abstract: A back contact heterojunction photoelectric conversion device, that obtain junctions that are nearly ohmic contacts by integrally forming a transparent conductive film including an electrode directly on a p-type amorphous silicon film and a transparent conductive oxide directly on an n-type amorphous silicon film. A method of manufacturing the device includes: integrally forming an oxide electrode layer on the n-type amorphous silicon film and the p-type amorphous silicon film; and applying plasma, under a condition that a mask is disposed on the transparent conductive film covering either the n-type amorphous silicon film or the p-type amorphous silicon film, to exposed portions of transparent conductive film.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Abstract: An overlay measuring method includes irradiating an electron beam onto a sample, including a multi-layered structure of overlapped upper and lower patterns formed thereon, to obtain an actual image of the upper and lower patterns. A first image representing the upper pattern and a second image representing the lower pattern are obtained from the actual image. A reference position for the upper and lower patterns is determined from a design image of the upper and lower patterns. A position deviation of the upper pattern with respect to the reference position in the first image and a position deviation of the lower pattern with respect to the reference position in the second image are calculated to determine an overlay between the upper pattern and the lower pattern.

Abstract: Pattern shrink methods comprise: (a) providing a semiconductor substrate comprising one or more layers to be patterned; (b) providing a resist pattern over the one or more layers to be patterned; (c) coating a shrink composition over the pattern, wherein the shrink composition comprises a polymer and an organic solvent, wherein the polymer comprises a group containing a hydrogen acceptor effective to form a bond with an acid group and/or an alcohol group at a surface of the resist pattern, and wherein the composition is free of crosslinkers; and (d) rinsing residual shrink composition from the substrate, leaving a portion of the polymer bonded to the resist pattern. Also provided are pattern shrink compositions, and coated substrates and electronic devices formed by the methods. The invention find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively.

Abstract: A semiconductor device according to an embodiment includes a SiC layer including a first region provided at a surface. The first region satisfies NA?ND<5×1015 cm?3 when a concentration of a p-type impurity is denoted by NA, whereas a concentration of an n-type impurity is denoted by ND. The surface is inclined at 0 degrees or more and 10 degrees or less to a {000-1} face, or the surface having a normal direction inclined at 80 degrees or more and 90 degrees or less to a <000-1> direction. The device includes a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, and a second region provided between the first region and the gate insulating film. The second region has a nitrogen concentration higher than 1×1022 cm?3.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first buffer layer, a second buffer layer, a n-type transistor structure, and a p-type transistor structure. The first buffer layer having a first germanium concentration is formed on a substrate. The second buffer layer having a second germanium concentration is formed on the substrate, the second germanium concentration being larger than the first germanium concentration. The n-type transistor structure is formed on the first buffer layer, and the p-type transistor structure is formed on the second buffer layer.