Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

Abstract: A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemFETs), depositing a dielectric layer over the chemFETs in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemFETs, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemFETs. The protective layer is at least one of a polymer, photoresist material, noble metal, copper oxide, and zinc oxide. The protective protective layer is removed using at least one of sodium hydroxide, organic solvent, aqua regia, ammonium carbonate, hydrochloric acid, acetic acid, and phosphoric acid.

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Abstract: Provided is an image display device including: a light source part (200) for emitting coherent light; and a plurality of phase shift elements (301) arranged in two-dimensional directions, the device further including a phase shift part (300) for scanning the wavefront of the coherent light from the light source part (200) in two-dimensional directions, in which light is scanned in the two-dimensional directions by a phased array to thereby allow an observer to observe an image.

Abstract: An imaging device which does not include a color filter and does not need arithmetic processing using an external processing circuit is provided. A first circuit includes a first photoelectric conversion element, a first transistor, and a second transistor; a second circuit includes a second photoelectric conversion element, a third transistor, and a fourth transistor; a third circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor; the spectroscopic element is provided over the first photoelectric conversion element or the second photoelectric conversion element; and the first circuit and the second circuit is connected to the third circuit through a first capacitor.

Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

Abstract: According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to each other. Each of the first and second magnetoresistive elements includes a first magnetic layer, a first non-magnetic later on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer. Furthermore, the magnetic memory device further includes a fourth magnetic layer being in contact with the first and second magnetoresistive elements or in contact with conductive layers on the first and second magnetoresistive elements.

Abstract: There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) having a deep superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes a gate trench extending through a base having the second conductivity type into the drift region. In addition, the IGBT includes a deep superjunction structure situated under the gate trench. The deep superjunction structure includes one or more first conductivity regions having the first conductivity type and two or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the two or more second conductivity regions configured to substantially charge-balance the deep superjunction structure.

Abstract: The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.

Abstract: A gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.

Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Abstract: Provided is a thermal type airflow volume meter improving measurement accuracy, a method for manufacturing the same, and an adhesive sheet for use therein, the adhesive sheet divided into at least two or more per adherend and having a thickness of approximately 0.1 mm or less is divided to correspond to a shape of the adherend and generates or increases adhesion or stickiness by external energy.

Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.

Abstract: There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches.

Abstract: An array substrate and a display device. The array substrate comprises a common electrode line, a plurality of gate lines and a plurality of data lines which intersect with each other, and pixel units defined by neighboring in gate lines. A storage electrode line is provided, so that storage capacitance between the storage electrode line and the pixel electrode can compensate storage capacitance formed between the common electrode and the pixel electrode. The ability of charge retention of the pixel electrode can be increased, so that voltage of the pixel electrode is constant during display period of a frame, and the display effect of a picture is ensured.

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.