Abstract: This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (TFT) characteristics. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. The p-type metal oxide films may be hydrogenated such that they have a hydrogen content of at least 1018 atoms/cm3, and in some implementations, at least 1020 atoms/cm3, or higher. Examples of hydrogenated p-type metal oxide films include hydrogenated tin (II)-based films and hydrogenated copper (I)-based films. The TFTs may be characterized by having one or more TFT characteristics such as high mobility, low subthreshold swing (s-value), and high on/off current ratio.

Abstract: The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.

Abstract: A method comprises forming a control gate structure over a substrate, depositing a memory gate layer over the substrate, applying a first etching process to the memory gate layer to form a memory gate structure, wherein, after applying the first etching process, a remaining portion of the memory gate layer is an L-shaped structure, forming a first spacer along a sidewall of the memory gate structure and forming a second spacer over the memory gate structure.

Abstract: A method comprises forming a memory gate structure adjacent to a control gate structure over a substrate, wherein a charge storage layer is between the memory gate structure and the control gate structure and a top surface of the memory gate structure is covered by a gate mask layer, forming a first spacer along sidewalls of the memory gate structure and the gate mask layer, wherein a sidewall of the memory gate structure is fully covered by the first spacer, applying an etching process to the charge storage layer to form an L-shaped charge storage layer and forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

Abstract: Methods, articles of manufacture and systems for creating new nanoscale two dimensional materials comprising designed arrays of lateral or vertical heterojunctions may be fabricated by first lithographically masking a 2D material. Exposed, or unmasked, regions of the 2D material may be converted to a different composition of matter to form lateral or vertical heterojunctions according to the patterned mask. PLD and high kinetic energy impingement of atoms may replace or add atoms in the exposed regions, and a plurality of the exposed regions may be converted concurrently. The process may be repeated one or more times on either side of the same 2D material to form any suitable combination of lateral heterojunctions and/or vertical heterojunctions, comprising semiconductors, metals or insulators or any suitable combination thereof. Furthermore, the resulting 2D material may comprise p-n, n-n, p-p, n-p-n and p-n-p junctions, or any suitable combination thereof.

Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via.

Abstract: The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.

Abstract: The embodiment of the present disclosure provides a phosphor improved in the emission intensity maintenance ratio without impairing the emission intensity. The phosphor is a silicofluoride phosphor and shows an IR absorption spectrum satisfying the conditions of 0?I2/I1?0.01 and 6.7?(I3/I1)/CMn. In those conditional formulas, I1, I2 and I3 are intensities of the maximum peaks in the ranges of 1200 to 1240 cm?1, 3570 to 3610 cm?1 and 635 to 655 cm?1, respectively, and CMn is a weight percent of Mn contained the phosphor.

Abstract: A nitride semiconductor device includes: a stacked structure portion having an active region; first and second main electrodes extending in a first direction; and a lead-out line (second lead-out line) electrically connected to the second main electrode and extends to one side in the first direction. The first main electrode has a first tip at an end which is on the side to which the lead-out line extends. The second main electrode has a second tip at an end which is on the side to which the lead-out line extends, and has, at a second tip-side in the first direction, a tapered portion having a width in a second direction which decreases with decreasing distance to the second tip. The lead-out line has a region projecting in the second direction from the tapered portion, and the first tip does not project further in the first direction than the second tip.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Abstract: The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting structure, and a heat spreader. The substrate core has a top surface and a bottom surface opposite the top surface of the substrate. The at least one connecting structure extends through the substrate core from the top surface of the substrate core to the bottom surface of the substrate core. And the heat spreader extends through the substrate core from the top surface of the substrate core to a bottom level that is below the bottom surface of the substrate core.

Abstract: The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.

Abstract: An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

Abstract: The re-combination center introduction region has re-combination centers introduced therein so that a density of the re-combination centers in the re-combination center introduction region is higher than a density of re-combination centers in a periphery of the re-combination center introduction region. The re-combination center introduction region continuously extends from the diode region to the peripheral region along a longitudinal direction of the diode region.

Abstract: An organic light-emitting display device includes a first substrate, a second substrate, a sealing adhesive layer, an organic light-emitting device and a touch sensing device. The first substrate and the second substrate are disposed opposite to each other. The sealing adhesive layer is disposed between the first substrate and the second substrate in a peripheral region. The organic light-emitting device is disposed on the second substrate in a display region, and the sealing adhesive layer surrounds the organic light-emitting device. The touch sensing device is disposed on the first substrate and includes a touch sensing electrode array and a plurality of sensing wires electrically connected to the touch sensing electrode array, respectively, and the sensing wires are disposed along the peripheral region at at least one side of the display region and over the sealing adhesive layer.

Abstract: A spring-mass system including a support, a mass mobile with respect to the support, at least one first and one second spring connecting the mass to the support allowing a displacement of the mass relative to the support along a first direction, the first spring being the symmetrical of the second spring with respect to an axis, each first and second spring comprising at least first and second series-connected beams arranged in zigzag, and a first closed frame surrounding the mass, at a distance from the mass and the support, each first beam having a first end connected to the support and a second end attached to the first frame and each second beam having a third end attached to the first frame and a fourth end connected to the mass.

Abstract: A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A display device in an embodiment according to the present invention includes a first substrate, a second substrate opposing the first substrate, and a transistor provided in the first substrate, a scanning signal line, a video signal line, and a pixel electrode that are electrically connected to the transistor, and a first insulating layer. The thickness of the first substrate is 0.3 mm or less, the first insulating layer contacts the first substrate, and is provided between the first substrate and the transistor, and the first insulating layer includes an organic insulating layer.