Abstract: A high-Q spiral inductor structure that utilizes a three-layer substrate, and methods of manufacturing the structure, are provided. The three-layer substrate is utilizable for CMOS circuits while at the same time minimizing eddy current induction and increasing the inductor quality factor Q of the structure.

Abstract: A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Abstract: A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Abstract: An insulation layer 12 is formed on a semiconductor substrate 11 and has a groove 12a for formation of a wiring layer 15 in a predetermined region. A barrier metal is formed on an inner wall of the groove 12a and prevents diffusion of atoms constituting the wiring layer 15, into the insulation layer 12. A seed layer 14 is formed on the barrier metal 13 formed at the bottom of the groove 12a and serves as a kernel of crystal growth when forming the wiring layer 15. The seed layer has crystal orientation of (1 1 1) as a dominant. The wiring layer is formed to bury the groove 12a. Moreover, the wiring layer has crystal orientation of (1 1 1) as a dominant, which suppresses electromigration.

Abstract: Methods are disclosed for forming Group III-arsenide-nitride semiconductor materials. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V crystals varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V crystals can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.

Abstract: An exemplary embodiment of the present invention discloses a method for forming a storage capacitor for a memory device, by the steps of: forming a bottom electrode of the storage capacitor over a BoroPhosphoSilicate Glass (BPSG) layer; forming a storage capacitor dielectric layer over the bottom electrode, the storage capacitor dielectric layer consisting of a nitride layer that is 50 Å or less in thickness; exposing the nitride dielectric layer to heat during a first stage rapid thermal oxidation step at a first temperature range that is equal to or greater than a reflow temperature required to reflow the BPSG layer; exposing the nitride dielectric layer to wet oxidation during a second stage rapid thermal oxidation step, the second stage rapid thermal oxidation step is performed at a second temperature ranging from 810° C. to 1040° C.

Abstract: A method for forming a passivation layer on at least one copper conductive element in a semiconductor structure and the devices formed are described. In the method, after a top surface of a semiconductor device that contains copper conductors embedded in an insulating layer is first planarized by a chemical mechanical polishing method, an etching process is conducted to create a stepped or corrugated surface between the surface of the copper conductor and the surface of the insulating layer, so that when a passivation layer is later deposited on top of the semiconductor structure, the same stepped or corrugated surface is reproduced in the passivation layer and thus providing a mechanical interlock between the passivation layer and the copper conductor for preventing adhesion failure or peeling of the passivation layer from the surface of the semiconductor structure.

Abstract: The present invention provides a method of easily planarizing the uneven surface of a substrate having an uneven surface. This method comprises the steps of forming a coating film containing spherical fine particles on a surface of a smooth substrate; sticking the surface of the smooth substrate provided with the coating film containing spherical fine particles to the uneven surface of a substrate having an uneven surface; and transferring the coating film containing spherical fine particles to the uneven surface of the substrate so that the uneven surface is planarized.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: A method for forming a metal line in a semiconductor device, in which a resolution is improved for securing a design rule and minimizing a difference of critical dimensions, including the steps of (1) forming a first insulating film and a second insulating film on a substrate, (2) etching the second insulating film to form a second insulating film pattern, (3) depositing a third insulating film on the second insulating film pattern, (4) removing the second insulating film pattern, and (5) forming a metal line layer in a region having the second insulating film pattern removed therefrom.

Abstract: In a method of fabricating a semiconductor device, a plurality of MOS devices are formed on a semiconductor substrate each with a source, a drain, and a gate electrode. A first insulating layer is formed on the semiconductor substrate with the MOS devices. A moat pattern is formed on the first insulating layer such that the portions of the first insulating layer placed at device isolation areas are exposed to the outside. Trenches are formed at the semiconductor substrate through etching the first insulating layer and the underlying semiconductor substrate using the moat pattern as a mask. The semiconductor substrate is partially etched by a predetermined depth. The trenches are filled up through forming a second insulating layer on the etched portions of the semiconductor substrate, and on the first insulating layer.

Abstract: A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area. The floating gate region is obtained by depositing and defining a semiconductor material layer through a floating gate mask. The floating gate mask has an opening with an internally delimiting side extending at a preset distance from a corresponding externally delimiting side of the mask, and the semiconductor material layer is removed laterally at the external and internal delimiting sides so that the tunnel area's length is defined, by the floating gate mask alone.

Abstract: The semiconductor device comprises an insulating film in which penetrating holes are formed, a semiconductor chip having electrodes, a wiring pattern adhered by an adhesive over a region including penetrating holes on one side of the insulating film and electrically connected to the electrodes of the semiconductor chip, and external electrodes provided on the wiring pattern through the penetrating holes and projecting from the surface opposite to the surface of the substrate on which the wiring pattern is formed. Part of the adhesive is drawn in to be interposed between the penetrating holes and external electrodes.

Abstract: A method of measuring at least one parameter associated with a portion of a sample having formed thereon one or more structures with at least two zones each having an associated zone reflectance property. The method includes the steps of illuminating the zones with broadband light, and measuring at least one reflectance property of light reflected from the at least two zones. The measurement includes a substantial portion of non-specularly scattered light, thereby increasing the quality of the measurement. The method further includes the step of fitting a parameterized model to the measured reflectance property. The parameterized model mixes the zone reflectance properties of the zones to account for partially coherent light interactions between the two zones.

Abstract: A method for forming a dual oxide layer on a silicon substrate provides that layer having varying thicknesses by using a damage layer formed on the silicon substrate, or a silicon nitride layer deposited on the silicon substrate. The damage layer is formed on the silicon substrate by dry etching a designated part of the silicon substrate, and the dual oxide layer is formed by using the properties of SiO2 by which the oxide layer growth speed on the damage layer is slower than that on the silicon substrate. A pattern of the damage layer is defined by photolithography, and the damage layer having a depth of about 20 to 5,000 Å is formed using CF4, CHF3, or Ar gas at a pressure of 900 mTorr or less, or using Cl2 or HBr. In the preoxidation cleaning step, a solution containing NH4F, HF, and H2O, a standard solution containing NH4OH, H2O2, and H2O, and/or HF are used.

Abstract: A method for fabricating an integrated electronic circuit includes producing electrically active elements in the region of one plane. At least one insulation layer and at least one contact-making layer are applied on the electrically active elements, and subsequently at least one connecting wire is applied to the contact-making layer. The contact-making layer is produced in such a way that the contact-making layer has a thickness which is at least 10% of the radius of the connecting wire. An integrated electronic circuit is fabricated with the aid of the method.

Abstract: In a semiconductor memory device production method for a semiconductor memory device having a capacitor formed by a high dielectric insulation film and a noble metal upper electrode successively formed on a noble metal lower electrode, the formation of the capacitor is followed by anneal in a gas mixture atmosphere of oxygen concentration of 0 to 5% and nitrogen at temperature of 300 to 400 degrees C. This enables to reduce the leak current at room temperature and suppress leak current increase during a high temperature operation.

Abstract: A method of forming a double gate metal-oxide-semiconductor field effect transistor (MOSFET). The method includes planarizing a backgate mesa stack of a backgate using chemical mechanical polishing (CMP) to isolate the backgate mesa. A topgate mesa stack is formed and patterned. The backgate is trimmed using the topgate as a mask to transfer a topgate pattern to the backgate. Then, the trimmed backgate is isolated. In one particular embodiment, CMP is used to isolate and planarize the trimmed backgate.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, parad.ium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.