Abstract: A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D<0.4(−100R+7)−1(−230 T+14.5), wherein D is a width of an element formation region, T is a thermal oxidation amount of a groove in terms of microns, and R is a curvature radius at an end bottom portion of the groove, has excellent properties such as reduced in stress generated at bottom portions of grooves in a silicon substrate and not generating abnormal junction leakage current.

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract: A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

Abstract: A TiN film and an ARL-SiON film (plasma SiO2 film+plasma SiON film) are deposited on a metal interconnection layer. The film thickness and the film quality of the ARL-SiON film is optmized to minimize the reflectance factor of the metal interconnection layer, and the composition of the ARL-SiON film is so adjusted that the ARL-SiON film can be easily dissolved by a hydrofluoric acid in a later process. The multi-layer antireflection layer composed of the TiN film and the ARL-SiON film, and the underlying metal interconnection layer are continuously dry-etched in the same processing chamber. At this time, the basis of the etching gas is composed of a combination of chlorine based gases (Cl containing gas such as Cl2, BCl3, HCl) which is the same as that used for etching the metal film. Furthermore, when the etching gas composed of a combination of Cl2 and BCl3 is used, the mixing ratio of the etching gas is changed.

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract: A bit line structure for semiconductor devices, and a fabrication method thereof are provided. In this method, a first conductive film pattern, which fills a first contact hole and is used as a bit line, is formed on a first dielectric film pattern having the first contact hole formed on a semiconductor substrate. A lower part protecting layer pattern, comprised of an anti-reflectance coating (ARC) layer used in a process for patterning the first dielectric layer pattern, is formed on the interface between the first conductive layer pattern and the first dielectric layer pattern. A spacer for covering the sidewall of the first conductive film pattern is formed. An upper part protecting layer pattern comprised of an upper ARC layer is formed to cover the upper part of the first conductive layer pattern. A second dielectric layer pattern having a second contact hole is formed to cover the first conductive layer pattern.

Abstract: A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.

Abstract: This invention discloses a planarization method for semiconductor device. The planarization method includes the steps of: providing a semiconductor substrate in which metal patterns are formed with various pattern densities; depositing a porous oxide layer over the semiconductor substrate so as to cover the metal patterns; plasma-treating surface of the porous oxide layer; and polishing the plasma-treated porous oxide layer by chemical mechanical polishing.

Abstract: In a method of manufacturing a semiconductor device, after a lateral growth region 107 is formed by using a catalytic element 105 for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region 108 by a heat treatment. Thereafter, a gate insulating film 113 is formed to cover active layers 110 to 112 formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.

Abstract: In a method of coating a semiconductor wafer with a resin of the present invention, first, a semiconductor wafer is placed on a bottom surface of a cavity provided in a molding surface of a lower mold of a mold with its surface having a bump facing upward. Thereafter, a required amount of resin material is supplied to cavity, and a film for exposing the bump is applied to a molding surface of the upper one of the molds. In this state, molds are closed together. Resin material is heated to melt in cavity. Then, film is pressed against the bottom surface of cavity by a pressing member provided on the molding surface of the upper mold, so that film is abutted against a leading edge of bump in cavity. A pressure is applied to the resin in cavity through film, and the surface having the bump of semiconductor wafer is coated with resin. According to the method, pressing member is provided on the upper mold, so that melted resin does not enter a sliding portion.

Abstract: A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.

Abstract: The present invention relates to formation of air gaps in metal/insulator interconnect structures, and to the use of supercritical fluid (SCF)-based methods to extract sacrificial place-holding materials to form air gaps in a structure. Supercritical fluids have gas-like diffusivities and viscosities, and very low or zero surface tension, so SCF's can penetrate small access holes and/or pores in a perforated or porous bridge layer to reach the sacrificial material. Examples of SCFs include CO2 (with or without cosolvents or additives) and ethylene (with or without cosolvents or additives). In a more general embodiment, SCF-based methods for forming at least partially enclosed air gaps in structures that are not interconnect structures are disclosed.

Abstract: In forming an interconnection having a structure in which an Al interconnection is covered with an interlayer insulating film, for the purpose of preventing voids to be created in the Al interconnection layer, together with suppressing the current leakage owing to the generation of etching residues, a multi-layered structure comprising a barrier layer, an Al interconnection metal layer, a Ti layer and an anti-reflection layer is formed on a semiconductor substrate having an insulating surface, and thereafter layers of said multi-layered structure are patterned, at least, down to the Ti layer into the shape of an interconnection pattern, and said patterned structure is heated so as to turn the Ti layer into an AlTi alloy layer and, then, the steps of growing an interlayer insulating film to bury said patterned interconnection, planarizing the interlayer insulating film and carrying out another heat treatment to degas the interlayer insulating film are performed.

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprising a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch resistant material, and etching the alternating layers thereby forming a capacitor structure having corrugated sides.

Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible cut points, 2) etching all possible cut points in a dielectric layer, 3) selectively exposing a second layer of photoresist with a non-precision targeting energy beam or mask to select the desired cut points. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.

Abstract: A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

Abstract: This invention relates to a MIS transistor and its manufacturing process. The process comprises the following steps: a) production of a dummy grid on a substrate, made of a material capable of resisting heat treatment, b) formation of self-aligned source and drain regions on the dummy grid, in the substrate, c) lateral coating of the dummy grid with an electrically insulating layer, d) elimination of the dummy grid and formation of a final grid made of a material with low resistivity, in the same position as the dummy grid. Application to the manufacture of hyper-frequency circuits.

Abstract: An integrated circuit device and method of making include an interconnect structure and a capacitor. The interconnect structure includes a metal line and a contact, and the capacitor includes upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The integrated circuit device provides a high-density capacitor having metal electrodes and which is compatible and integrated with dual damascene structures. As such, the capacitor is situated in a same level as a dual damascene interconnect structure.